EE210 Digital Electronics Class Lecture 10 April 08, 2009

1. EE210Digital ElectronicsClass Lecture 10April 08, 2009

2. Home Work No. 5 (Due April 15, 2009 ) Problems at the End Of Chapter 10. • Problem D10.25 • Problem D10.26 • Problem D10.46 • Problem D10.47

3. In This Class We Will Continue to Discuss: Complete CMOS Gates 10.3.9 Effects of Fan-in and Fan- out on Propagation Delay 10.4 Pseudo-NMOS Logic Ckts 10.5 Pass-Transistor Logic Ckts

4. 10.3.9 Effects of Fan-in and Fan-out • As compared to other MOS logic, CMOS logic requires two transistors (NMOS and PMOS) for each additional Input • This results in Increase in Chip Area and Total Effective Capacitance per gate hence Increase in Propagation Delay • Increase in number of in-put (fan-in) increases size and increase tp and due to that there is limit on fan-in of the NAND gate to 4. • For higher inputs clever logic design is required

5. 10.3.9 Effects of Fan-in and Fan-out • Increase in gate’s fan-out adds directly to its load capacitance and increases propagation delay • Thus apart from many advantages, CMOS suffers from increased circuit complexity when fan-in and fan-out are increased • In next two sections we shall study some simplified forms of CMOS logic that reduces this complexity, however, we will loose some advantages of CMOS

6. 10.4 Pseudo-NMOS Logic Ckts 10.4.1 Pseudo-NMOS Inverter Input is applied at QN gate and QP gate is grounded, thus QP acts as an active load for QN. Note that before even going into more details the advantage over CMOS is already obvious: One transistor (NMOS) for each input

7. 10.4.2 Static Characteristics • The static characteristics of pseudo-NMOS inverter can be derived in similar manner as we did for CMOS inverter • So the drain currents of QN and QP are: where Vtn = -Vtp = Vt and kn=kn’(W/L)n and kp=kp’(W/L)p • To Obtain VTC, we superimpose load curve (QP iD-vDS) on the QN iD-vDS characteristics for various values of vGS=vI

8. 10.4.2 Static Characteristics NOTE that: 1. QP has much lower saturation current than QN at vI=VDD. This is because pseudo-NMOS inverter usually designed so that kn is 4 to 10 times kp. In fact, r ≡ kn/kp determines all the breakpoints of VTC and noise margins. High value of r reduces VOL and widens NMs. 2. One tends to think of Qp as constant-current source, but it actually operates in saturation for only a small range of vO≤ Vt. Rest is in triode region

9. 10.4.2 Static Characteristics Now consider two extreme cases of vI: When vI=0, QN is cut off and QP is operating in the triode region with zero current and zero drain-source voltage. Point A, where vO=VOH=VDD, Static current is zero. When vI=VDD the operating point is E. Unlike CMOS here VOL is not zero – a disadvantage. Another disadvantage is that the gate conducts Istat in low output state, thus there will be static power dissipation: PD=IstatxVDD

10. 10.4.3 Derivation of VTC • VTC of pseudo-NMOS inverter has four regions labeled I thru IV corresponding to different modes of operation of QN and QP.

11. 10.4.3 Derivation of VTC Region I (Segment AB) vO = VOH = VDD Region II (Segment BC) Equating iDN and iDP and using kn=rkp and some manipulation

12. 10.4.3 Derivation of VTC Region III (Segment CD) Being short segment is not very important. Point D is vO = Vt .

13. 10.4.3 Derivation of VTC Region IV (Segment DE) Equating iDN and iDP and using kn=rkp results

14. 10.4.3 Derivation of VTC Finally, we use these equations to determine NML and NMH Since VDD and Vt are determined by the process technology the only parameter for controlling the values of VOL and the noise margins is the ratio r.

15. 10.4.4 Dynamic Operation • Similar procedure as CMOS inverter is used to find tPLH and tPHL for thepseudo-NMOS inverter and are given as: • Although these are identical to CMOS inverter, the pseudo-NMOS inverter has a special problem: Since kp is r times smaller than kn, tPLH will be r times larger than tPHL. Thus ckt exhibits asymmetrical performance.

16. 10.4.6 Gate Circuits Except for the load device, pseudo-NMOS gate circuit is identical to PDN of CMOS gate Note that NOR and NAND gates each require five transistors compared to eight in CMOS

17. 10.4.7 Concluding Remark • The pseudo-NMOS is particularly suited for applications in which the output remains high most of the time. Since gate dissipates static power only in low-output state, the static power dissipation in this application is low. • The propagation delay can be made as short as necessary for the output transition from high-to-low. • This type of application can be found in ROMs. Example 10.3

18. 10.5 Pass-Transistor Logic Ckts • A simple approach to implement logic functions is to use series and parallel combination of switches controlled by input logic variables to connect input and output nodes These switches can be NMOS transistor or pair of complementary MOS transistor connected as CMOS transmission gate configuration

19. 10.5 Pass-Transistor Logic Ckts • This provides simple form of logic circuit that is particularly suited for special logic functions and is frequently used in conjunction with CMOS logic to implement such functions efficiently • Because this form of logic utilizes MOS transistors in series path from input to output, to PASS or block signal, it is known as Pass-Transistor Logic (PTL) • As CMOS transmission gates are frequently used to implement switches in these logic circuits an alternative name as Transmission-gate logic. Generally both these names are used irrespective of actual switches • Although simple, PTL logic circuits design require care

20. 10.5.1 Essential Design Requirement • Essential requirement to design PTL circuit is to ensure that every ckt node has at all times a low-resistance path to VDD or ground. Switch S1 is used to form AND Function of its controlling variable B and variable A at the CMOS inverter output. Y of PTL is connected to input of another inverter. When B is Hi S1 closes and Y=A. Node Y will be connected to either VDD (if A is Hi) or to ground (if A is Low). But what happens when B is low and S1 opens? Node Y will now become high-impedance node. If vY was zero it will remain so. However, if it was VDD, it will be maintained by the charge on parasitic C, for only a time. Leakage current will slowly discharge C and vY will be lost.

21. 10.5.1 Essential Design Requirement Problem can be easily solved by establishing a low-resistance path for node Y that is activated when B goes low (S1 opens). In the improved design here another switch S2 is controlled by B (bar) And connects Y and ground.

22. 10.5.2 Operation with NMOS as SW Using NMOS as switch in PTL results in small area and small node capacitances. These advantages are achieved at the expense of serious shortcomings in both static characteristics and the dynamic performance of the circuit.

23. 10.5.2 Operation with NMOS as SW When vI goes to Zero

24. 10.5.2 Operation with NMOS as SW Technique to correct ‘Poor 1’

25. 10.5.3 Use of CMOS Transmission Gate as SW

26. 10.5.3 Use of CMOS Transmission Gate as SW

27. 10.5.4 Pass-Transistor Logic Circuit Examples

28. 10.5.4 Pass-Transistor Logic Circuit Examples

29. 10.5.4 Pass-Transistor Logic Circuit Examples