Riyadh Philanthropic Society For Science Prince Sultan College For Woman

1. Riyadh Philanthropic Society For Science Prince Sultan College For Woman Dept. of Computer & Information Sciences CS 251 Introduction to Computer Organization & Assembly Language Lecture 6 (Computer System Organization) Main Memory II

2. Outline • From Text Book: 2.2.5, 2.2.6, 3.3.5, 3.3.6 • Cache memories • RAMs • ROMS • Memory types comparison • Memory packaging and types Main Memory

3. Cache Memories • There is an imbalance between the speed of the CPU and that of the memory • The CPU will have to wait for many cycles before receiving a word from memory • The slower the memory, the more cycles the CPU will have to wait • Memory designers are using new technologies to increase the capacity of their chip not the speed • The problem is in economics not technology • To have the memory as fast as the CPU, it has to be placed at the same chip as the processor • This makes the chip larger and more expensive Main Memory

4. Cache Memories (Cont.) Cache memory = Small Fast memory • A compromise between size and speed has to be done • Small amount of fast memory • Large amount of slow memory Main Memory

5. Cache – Basic Idea • The most heavily used memory words are put in the cache • When the CPU needs a words, it looks in the cache first • If the word is not in the cache, then the CPU will go into main memory • If a substantial fraction of memory words is in the cache, then the access to the main memory is greatly reduced. • Thus, success or failure depends on what words are found in the cache Main Memory

6. Cache – Word Saving • Programs don’t access the memory words at random • If a given memory address is A, it is most probable that the next access will in the vicinity of A ( around A) • Examples: • Program instructions (except for branches and procedure calls) are fetched from consecutive locations in memory. • Most program execution time is spent in loops, in which a limited number of instructions are executed over and over. • The observation that the memory references made in any short time interval tend to use only a small fraction of the total memory is called the locality principle. Main Memory

7. CPU Main Memory Bus Cache Cache – Locality Principle • When a word is referenced, it along with its neighbors will be fetched from main memory to the Cache • This will allow for faster addressing of consecutive words • The cache is logically placed between the CPU and the main memory • Physically, there are several locations for it to be placed Main Memory

8. Locality principle (Cont.) Mean access time = c + (1 – h) m What happens if h approaches1? • If a word is read/written k times in a short time interval, it will need • 1 access to the main memory • k-1 access to cache • The larger k is, the better the overall performance is. • The calculation could be formalized using the following notations • c = cache memory access time • m = main memory access time • h = hit ratio, the fraction of all the references that could be found in the cache (h = (k-1)/k) • 1 – h = miss ratio Main Memory

9. Cache lines • Caches and main memories are divided up into fixed size blocks • The blocks inside the cache are called cache lines • When a word is missed in the cache the entire line will have to be fetched from memory, not just the word itself • Ex. • The cache line block is 64 bytes • If the word referenced is at address 261, • The line 256 to 316 will be pulled from main memory into the cache • Design of the cache is an increasingly important subject for high-performance CPUs Main Memory

10. Cache – Design Issues • Cost: The bigger the cache, the better is the performance, the higher the cost • Cache line size: Cache could be organized in several ways (Ex. 16 KB) • 1 KB lines with 16 bytes • 2 KB lines with 8 bytes • Cache Organization: How the cache keeps track of the word that is currently being fetched from memory. • Number of Caches : chips nowadays have • A primary cache on chip • A secondary cache off chip, but in the same package as the CPU chip • A third cache still further away Main Memory

11. Cache – Design Issues (Cont.) • Whether instructions and data are kept in same cache • Unified Cache : the data and instruction use the same cache (Von Neumann architecture) • Split Cache: The data and instruction each uses a separate cache (Harvard architecture) • In comparison between the Von- Neumann and the Harvard architectures: • The Von-Neumann is simpler and easier to build • Harvard allows for parallel access on data and instructions • The Harvard instruction cache doesn’t have to be written back to memory Main Memory

12. RAM – Random Access Memory • It is possible to both read data from memory and to easily and rapidly write new data into memory. • RAMs come in two varieties: • Static RAM = SRAM • Dynamic RAM = DRAM Main Memory

13. RAM – Types Main Memory

14. ROM – Read Only Memory • Nonvolatile data storage medium • The data in a ROM are inserted during its manufacturing through the use of a mask • Data can’t be erased or altered • Uses of ROM include system programs , cars, appliances, etc … • To change the program in the ROM the entire chip should be replaced • Cheaper than RAMs when placed in large orders Main Memory

15. ROM – Types • PROM (Programmable ROM): It can be programmed once in the field after it is manufactured through burning the fuses inside • EPROM (Erasable Programmable ROM): The data could be altered in the field through the exposure to UV light in special chambers • EEPROM(Electrically EPROM): The data could be erased and rewritten in the field by applying electric pulses instead of using special UV chambers • Flash memory: an enhanced form of EEPROM that wares out after 100,000 erasures. Main Memory

16. Memory Types Comparison Main Memory

17. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 512K x 8 Memory chip (4 Mbit) 4096K x 1 Memory chip (4 Mbit) D0 D1 D2 D3 D4 D5 D6 D7 D RAS CAS CS WE OE CS WE OE Memory Chip • For any memory size, there are several ways to organizing it • Ex. Two different organization of a 4 Mbit memory Main Memory

18. Memory Chip - Notation • Pins are set = Asserted • Some asserted High = set with high (1) current • no bar above pin name: i.e. CS • Some asserted LOW = set with low (0) current • bar above pin name: i.e. RD • When pins are not asserted, they are Negated. Main Memory

19. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 512K x 8 Memory chip (4 Mbit) D0 D1 D2 D3 D4 D5 D6 D7 CS WE OE Memory Chip Main Memory • 512K x 8 = 512 K words, each 8 bits wide. • 19 address lines are needed to address one of the 19 bytes available • 8 data lines are need for loading and storing the byte selected

20. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 512K x 8 Memory chip (4 Mbit) D0 D1 D2 D3 D4 D5 D6 D7 CS WE OE Memory Chip Main Memory • Computers usually have many memory chips • A signal is needed to select the needed chip • The selected chip only will respond, all others wont. • CS (Chip select) signal is provided for this purpose. • It is asserted to enable the chip

21. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 512K x 8 Memory chip (4 Mbit) D0 D1 D2 D3 D4 D5 D6 D7 CS WE OE Memory Chip Main Memory • A way is needed to distinguish read from write • WE (write Enable) is asserted to indicate that the data are being written rather than read • OE (output Enable) is asserted to drive the output signals. If it is not asserted, the output is disconnected from the chip

22. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 4096K x 1 Memory chip (4 Mbit) D RAS CAS CS WE OE Memory Chip Main Memory • 4096K x 1 is organized as a 2048 x 2048 matrix of 1 bit cells. • To address the chip • A row is selected by putting its 11-bit number on the address pin, and RAS (Row address strobe) is asserted • A column is selected by putting its 11-bit number on the address pin, and the CAS (column Address Strobe) is asserted • Data is then outputted one bit at a time

23. Memory Chip Main Memory • To build a memory with 32-bit word from 4096K x 1 chips requires 32 chips in parallel. • To build a memory with 32-bit word from 512K x 8 chips requires only four chips in parallel. • To avoid having 32 chips for memory, most chips now have chip families with 1, 4, 8, and 16 bit width.

24. Memory Packaging & Types Main Memory • Until the early 1990s, memory was manufactured, bought, and installed as single chips. • Chip densities were from 1K bits to 1M bits and beyond, but each chip was a separate unit. • At present, a different arrangement is often used. • A group of chips, typically 8 or 16, is mounted on a tiny printed circuit board and sold as a unit. • This unit is called a SIMM (Single Inline Memory Module) or a DIMM (Dual Inline Memory Module), depending on whether it has a row of connectors on one side or both sides of the board.

25. SIMM with 32 MB 4-MB memory chip Connector Main Memory • A typical SIMM configuration might have eight chips with 32 megabits (4 MB) each on the SIMM (+ 2 control chips). • Many computers have room for four modules, giving a total capacity of 128 MB when using 32-MB SIMMs. • Often these SIMMs can later be replaced by 64-MB or larger SIMMs as needed.