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241-440 Computer System Design Lecture 3

241-440 Computer System Design Lecture 3. Wannarat Suntiamorntut. Arithmetic for Computer. Implementing the Architecture. The numbers. Binary number (base 2) numbers are finite ( overflow ) fraction and real number

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241-440 Computer System Design Lecture 3

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  1. 241-440Computer System DesignLecture 3 Wannarat Suntiamorntut 241-440 W.S.@2009

  2. Arithmetic for Computer • Implementing the Architecture 241-440 W.S.@2009

  3. The numbers • Binary number (base 2) • numbers are finite (overflow) • fraction and real number • negative number e.g., No MIPS subi instruction, addi can add a negative number 241-440 W.S.@2009

  4. Possible Representations Sign Magnitude One’s complement Two’s complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 Negative and Invert are different! 241-440 W.S.@2009

  5. Addition & Subtraction • 7 - 6 {0111 - 0110} = 0001 • two’s complement 0111 + 1010 = 0001 • Overflow n-bit does not yield an n-bit number 0111 + 0001 1000 241-440 W.S.@2009

  6. Detecting overflow • No overflow when add positive&negative • No overflow when signs are the same for subtraction • Overflow occur when : - add two positives yield a negative - add two negative gives a positive - subtract negative from positive and get negative - subtract positive from negative get a positive 241-440 W.S.@2009

  7. Effect of Overflow • Exception occur (Interrupt) - control jumps to predefined address for exception - Interrupted address is saved • Don’t always to detect overflow - New MIPS instructions: addu, addiu ... 241-440 W.S.@2009

  8. ALU • Build ALU support andi, ori instructions 241-440 W.S.@2009

  9. Multiplexor • Select one of the inputs to be output, base on control input 241-440 W.S.@2009

  10. ALU for Addition instruction • Cout = ab + bcin + acin • Sum = a xor b xor cin 241-440 W.S.@2009

  11. ALU for Subtraction instruction • Two’s complement approach : just negative b and ADD 241-440 W.S.@2009

  12. Supporting slt 241-440 W.S.@2009

  13. 241-440 W.S.@2009

  14. MIPS Arithmetic Instruction format 241-440 W.S.@2009

  15. Conclusion ALU in MIPS • Use multiplexor to select output we want • efficiently perform subtraction using two’s complement • replicate 1-bit ALU to 32-bit ALU 241-440 W.S.@2009

  16. Computation Problem :fast adder • 32-bit ALU faster than 1-bit ALU? • Carry-lookahead adder g = ab, p = a + b c1 = g0 + p0c0 c2 = g1 + p1c1c2 c3 = g2 + p2c2c3 ... 241-440 W.S.@2009

  17. 241-440 W.S.@2009

  18. Part II : Lecture III 241-440 W.S.@2009

  19. Multiplication 0010 (multiplicand) x 1011 (multiplier) ???? 241-440 W.S.@2009

  20. Unsign Combinational Multiplier 241-440 W.S.@2009

  21. Multiplication : First Version (Unsign) 241-440 W.S.@2009

  22. Multiplication : First Version (contd.) 241-440 W.S.@2009

  23. Analyze First Version • 1 clock per cycle • 50 % of bit in multiplicand always = 0 => 64-bit adder is wasted • 0’s inserted in left of multiplicand as shifted => lead significant bits of product never changed once formed 241-440 W.S.@2009

  24. Multiplication : Second Version 241-440 W.S.@2009

  25. Multiplication : Second Version (Contd.) 241-440 W.S.@2009

  26. Analyze Second Version • Product register wasted space that exactly matches size of multiplier Combine Multiplier register and Product register 241-440 W.S.@2009

  27. Multiplication : Third Version 241-440 W.S.@2009

  28. Multiplication : Third Version (Contd.) 241-440 W.S.@2009

  29. Analyze Third Version • 2 steps per bit because multiplier & product combined • MIPS registers Hi, Lo are left and right half of product 241-440 W.S.@2009

  30. Booth’s Algorithm 241-440 W.S.@2009

  31. Example : 2 x 7 241-440 W.S.@2009

  32. Example : 2 x -3 241-440 W.S.@2009

  33. Shifter : 2 kinds 241-440 W.S.@2009

  34. Part III : Lecture III 241-440 W.S.@2009

  35. Divide 241-440 W.S.@2009

  36. Divide : First Version 241-440 W.S.@2009

  37. Divide : First Version (Contd.) 241-440 W.S.@2009

  38. Analyze First Version • 50% bits in divisor always 0 =>1/2 of 64-bit adder is wasted => 1/2 divisor is wasted • 1 step cannot produce a 1 in quotient bit => Switch order to shift first 241-440 W.S.@2009

  39. Divide : Second Version 241-440 W.S.@2009

  40. Divide : Second Version (Contd.) 241-440 W.S.@2009

  41. Analyze Second Version • Eliminate Quotient register by combining with Remainder as shifted left 241-440 W.S.@2009

  42. Divide : Third Version 241-440 W.S.@2009

  43. Divide : Third Version (Contd.) 241-440 W.S.@2009

  44. Analyze Third Version Do Analyze by yourself 241-440 W.S.@2009

  45. Floating Point : IEEE754 241-440 W.S.@2009

  46. 1 01111110 1000 0000 0000 0000 0000 000 S E M 1-bit 8-bit 23-bit Floating-point Representation • -0.75 = -3/4 = -3/22 = -11/ 22 = -0.11 = -1.1x 2-1 = (-1)s x (1 + signifiand) x 2 (exponent-127) = (-1) x (1+.1000 0000) x 2(126-127) 241-440 W.S.@2009

  47. Floating-point Addition 9.999 x 101 + 1.610x10-1 • Step1 : Change exponent as : 1.610 x 10 -1 = 0.016 x 101 • Step2 : Add significands 9.999 (10) + 0.016 (10) 10.015 (10) Sum = 10.015 x 101 241-440 W.S.@2009

  48. Floating-point Addition 9.999 x 101 + 1.610x10-1 • Step3 : correct it (normalization) : 10.015 x 10 1 = 1.0015 x 102 • Step4 : Four digits for significand 1.002 x 102 241-440 W.S.@2009

  49. Example Floating-point Addition 0.5 + (-0.4375) 0.5 = 1/2 = 1/21 = 0.1 x 20 = 1.00 x 2-1 -0.4375 = -7/16 = -7/24 = - 0.0111 = -1.110 x 2-2 step 1 : -0.111 x 2-1 step 2 : 1.0x 2-1 + (-0.111 x 2-1)=0.001 x 2-1 step 3 : 1.0 x 2 -4 step 4 : 0.0625 241-440 W.S.@2009

  50. Multiplication Floating-point Study in Text Book by yourself. 241-440 W.S.@2009

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