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VARIABLE SWING Optimal Parallel LINKs Minimal Power, Maximal density for parallel links configurations Claudia P. Barrera advisor: fouad kiamilev PhD committee: Allen Barnett guang gao mayra sarmiento. Ph.D. Dissertation Defense. Outline. Outline - Introduction. Motivation. Motivation.

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VARIABLE SWING Optimal Parallel LINKsMinimal Power, Maximal density for parallel links configurationsClaudia P.Barreraadvisor: fouad kiamilevPhD committee:Allen Barnettguang gaomayra sarmiento

Ph.D. Dissertation Defense


Outline


Outline - Introduction


Motivation


Motivation

  • Mobility

  • Mobile devices require low power, high data rates

    • Increasing multimedia applications

    • Higher definition displays

    • Smaller sizes

    • Battery life


Motivation

  • Size

  • Transistor size still decreasing

  • Moore’s Law still valid

  • Higher computational capabilities on-chip but interconnect requirements constrain the size of the devices


Motivation

Source: Intel Corporation - http://www.intel.com/technology/timeline.pdf


Motivation

  • Speed

  • Required higher data rates

    • Multimedia applications

    • High Performance Computing

    • Off-chip speed is the bottleneck for high speed communications

2003 ITRS (International Technology Roadmap for Semiconductors) roadmap for on-chip and off-chip speed.

Taken from http://www.ieee.org/organizations/pubs/newsletters/leos/oct04/summer.html


Problem Statement

POWER SAVINGS

  • Design Stage

    • Need of communication between A and B

      • Length

      • Speed

      • Power

MAXIMUM LINE LENGTH / SPEED

8 – 16mA - TX current

3.5mA - TX current

0.1mA - TX current

CML

LVDS

WhisperBus

Standard

Fixed TX Power

A

B

Communication

If length is long, a high TX

power is OK

But if the distance between

A and B is short, there will be a

Waste of Power.


Problem Statement

  • Design Stage

    • Maximum data rate allowed in the communication

      • Serial

      • Parallel

Data Rate: X

Data Rate: 4X

P

P

SERDES

Serializer - Deserializer

B

A

SERDES

SERDES

P

P


Problem Statement

  • Design Stage

    • Maximum data rate allowed in the communication

      • Serial

      • Parallel

Data Rate: X

Data Rate: 4X

P

P

SERDES

Bandwidth Increment

4X

4X

P

P

A

B

P

P

P

P

4X

4X

Then, what is the problem with parallel links?


Problem Statement

  • Space…

1

2

A

B


Problem Statement

  • Space…

A

B


Problem Statement

  • Space…

A

B

A

Bandwidth Limitation by maximum number of wires that can be routed


Previous Work

  • Optimization based on free parameters

    • Geometry

w

d

t

h

εr


Previous Work

  • 3D approach to eliminate crosstalk

  • Not feasible for a PCB


Previous Work

  • Jitter equalization technique that induces a data dependent delay to compensate for crosstalk jitter

  • Quantification of crosstalk-induced jitter from the mutual capacitance and inductance between two adjacent lines


Serial Power Optimization TechniqueVSMPL

POWER OPTIMIZATION ALGORITHM

BASED ON AN ACCELERATED BIT

ERROR RATIO (BER) MEASUREMENT

  • Set transmitter power to where BER~10-4

  • Increment power setting

  • Measure current BER

  • Repeat steps 2 and 3 several times

  • Fit a line through the data points

  • Estimate the transmitter power setting required to achieve the target BER

    J. Kramer


Serial Power Optimization TechniqueVSMPL

BER 2

BER 1

Accelerated BER Tester

Power setting 1

Power setting 2

Power set to 3

Power 3 =F(BER1,BER2)


VSMPL in a bus configuration

Accelerated BER Tester

1

2

BER increases

1

2

1

2

BER increases


Contribution of this work

  • Based on accelerated BER measurement:

    • Simple technique that reduces crosstalk

      • Novel technique using anti-coupling capacitors

      • Up to 87% reduction

    • Reflections are minimized

      • Termination resistor is adjusted dynamically

  • Once crosstalk and reflections are minimized:

    • Channels can be treated as serial links.

    • Serial power optimization technique can be applied

MINIMAL POWER, MAXIMUM DENSITY FOR A PARALLEL LINK


Outline - Crosstalk


Transmission line modeling

w

t

εr

h

Microstrip

Stripline

Wire Pair


Transmission line modeling


Coupling between transmission lines

1

2

εr

M

M


Coupling between transmission lines

Aggressor

Victim

Near End

Far End

Near End

Far End


Coupling between transmission lines

Vb

Time

RT

Far End noise

Near End noise

RT: Rising Time

TD: Time Delay

Vb

Near End

Far End

TD

Time

RT

2 x TD


Coupling between transmission lines

C14

C24

C13

C12

C23

C34

1

2

3

4

C11

C22

C33

C44


Differential Signaling

V1

1

+

Vo=V1-V2

2

-

V2

Advantages:

Tolerance to ground offsets

Low voltage

High immunity to common noise


Crosstalk in differential signaling

The problem of crosstalk in differential signaling is that generates a non common noise.

The effect of electromagnetic fields is higher on the closest line

V1-V2

(V1+b*Vn)-(V2+d*Vn)

d* > b*

V1

V2

Vn

V1

V2

Vn

Differential pair with a quiet line routed closely

Noise effect in a differential pair when an active line is routed closely


Crosstalk in differential signaling

C14

Aggressor

Victim

C24

+

-

+

-

C13

C23

Transmission lines are linear systems

Superposition can be applied

VV+

VV-

VA+

VA-

Victim

Aggressor

VA+=-VA-

VV+=VA+*(C13)+VA-*(C14)

VV-=VA+*(C23)+VA-*(C24)

VV=VV+-VV-


Anti-Coupling Capacitances

C14

C24

Using superposition principle…

C13

VV+=VA+*(C13)+VA-*(C14)

C23

+VA-*(Anti-C13)+VA+*(Anti-C14)

+

-

+

-

VV-=VA+*(C23)+VA-*(C24)

VA+=-VA-

VV=VV+-VV-

Anti-C24

+VA-*(Anti-C23)+VA-*(Anti-C24)

Anti-C14

Anti-C23

Anti-C13


Reflections

  • Reflections happen when the transmission line is not matched.

Output impedance

Characteristic Impedance Zo

Termination

Impedance


Optimization algorithm

BERT

+

  • Tune the termination resistor on the receiver based on the BER measurement on the link at low power.

  • Tune the anti-coupling capacitances:

    • Turn on the victim line at low power (so that BER is in the order of 10-4)

    • Turn on one neighbor at the highest power. The BER in the victim line will increase due to crosstalk noise.

    • Tune anti-coupling capacitance until minimum BER is reached.

  • Review impedance matching for the line. Repeat 1 and 2 until stable.

  • Apply serial power optimization to each line.

Anti-C23

-

Anti-Cb

Anti-C23

+

-


Outline – Testing, Simulation Platforms and Results


Testing Platform

BERT

Labview Card

Anritsu Digital Data Analyzer

RX

TX

PRBS

Generator


Testing Results


Testing Results

35uA

48uA

63uA


Simulation Platform

W-Element Matrix


Experiments setup

6.5mils

4mils

Aggressor

4mils

Victim

5.7 mils

100mm


Extracted transmission line parameters


Transistor level simulation


Simulation Platform


Effect of anti-coupling capacitors

  • Differential pairs routed as close as manufacturing technology allows

    • One aggressor

    • One victim

  • Measured the differential voltage on the victim and report the highest noise (voltage)

  • Placed 4 capacitors and started to change the value of one of them until the minimum crosstalk was reached.


Effect of anti-coupling capacitance

  • By adding the anti-coupling capacitance, the crosstalk is reduced up to 78%.


Required spacing to achieve same performance

  • Increase spacing between the 2 lines by 1X and measure the highest noise.

  • Repeat previous step until performance of anti-coupling capacitors is reached


Required spacing to achieve same performance

  • To achieve the same crosstalk reduction, the spacing between differential lines must be 6X

Anti-coupling capacitances performance


FFT of the signal induced by crosstalk In the quiet line

  • -Minimum spacing between differential

  • channels

  • -- 5X spacing between differential

  • channels

  • -- Minimum spacing between differential

  • Channels using anti-coupling cap

Power noise on the victim line is reduced significantly when an anti-coupling capacitance is used. The effect of adding the anti-coupling capacitors is actually better than spacing the channels by the rule of thumbs given by the literature.


Far end noise – time domain

Aggressor

-- No anti-coupling capacitances

-- Effect of anti-coupling capacitances in time domain

Victim


Effect of anti-coupling capacitances in induced jitter

-- No anti-coupling capacitances

-- Effect of anti-coupling capacitances

140ps

17ps


Optimization of anti-coupling capacitances

Anti-C13 = Anti-C24 = 0.8pF

Anti-C14 and Anti-C23

Variable


Optimization of anti-coupling capacitances

Minimum crosstalk noise power : 0.7mW

Without the anti-coupling capacitances: 3.3mW

79% less noise power


Optimization of anti-coupling capacitances

Symmetrical response, and minimum crosstalk noise in both channels:

Anti-C13 = Anti-C24

Variable

Anti-C14 = Anti-C23

Variable


Optimization of anti-coupling capacitances

Minimum crosstalk noise power : 0.4mW

Without the anti-coupling capacitances: 3.3mW

87% less noise power


Impact of anti-coupling capacitances

The use of anti-coupling capacitances allow routing of high speed paths as close as possible without performance impact.

Each channel is transmitting at 10Gbps using the minimum space allowed by the manufacturer.


Outline - Conclusions


Conclusions

  • Optimize the signal integrity and power of a differential parallel link

  • Higher bandwidth-per-unit-area

  • Anti-coupling capacitors cancel out the effect of mutual impedances in the transmission lines.

  • Implementation increases six times the bandwidth-per-unit-area in a parallel link communication

  • Accelerated BER measurement gives a new perspective to electrical interconnect designers since it opens new possibilities of dynamically improving performance of the link according to its specific needs.


Future Work

  • Implementation on FPGA:

    • capability of adjusting the power of the transceivers, or selecting a proper termination resistor is given, e.g. Rocket IO.

    • BERT is a given component, easy implementation in VHDL.

    • Addition of the anti-coupling capacitances off-chip.


Future Work

  • Improvement of the optimization methodology

    • Faster convergence by optimization techniques

    • More capacitances for longer paths can be studied

    • Effect of capacitances on the transmission line’s bandwidth

  • The work can be extended for:

    • Single ended configurations

    • On-chip communication


Publications

  • C.P. Barrera, F. Kiamilev, J. Kramer, J. T. Ekman, - Testing of the Next Generation variable-swing Multi-gigabit Chip-to-Chip Interconnect for Bus Configurations, The 18th Annual IEEE Workshop on Interconnections within High Speed Digital Systems, May 2007, Santa Fe, NM

  • C.P. Barrera, J. Helou, J. Kramer, J. Ekman, N. Waite, Prof. F. Kiamilev, “Trusted Foundry ASIC designs - University of Delaware” presented at the DARPA and OSD Trusted Foundry Circuit Designers Meeting, September 12-13, 2007 in Burlington, VT.

  • J. Kramer, C.P. Barrera, F. Kiamilev - Accelerated Bit Error Rate Measurement Technique for Multi-link Gigabit interconnects, In preparation for TCAS - IEEE Transactions on Circuits and Systems I

  • C.P. Barrera, F. Kiamilev, N. Waite, - Variable Swing Optimal Parallel links – Minimal power, Maximal density for parallel links, Accepted for The 20th Annual IEEE Workshop on Interconnections within High Speed Digital Systems, May 2009, Santa Fe, NM

  • C.P. Barrera, F. Kiamilev, N. Waite – Crosstalk Cancellation Using Anti-Coupling Capacitances, In preparation for JQE – IEEE Journal in Quantum Electronics


Acknowledgments

  • Dr. Kiamilev

  • Committee Members:

    • Dr. Barnett

    • Dr. Gao

    • Dr. Sarmiento

  • Dr. Kramer, Jirar Helou, Nick Waite

  • Andres

  • CVORG

  • Friends

  • Family in Colombia

  • God


Questions?

Thank you


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