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Dissertation Defense Presentation

Dissertation Defense Presentation. Topic: A study of functional architecture of the Internet Protocol-Television (IPTV) and VLSI realization of streaming server controller Committee Members: Presented by: Dr. Subbarao V. Wunnava (Major Advisor) Vivekananda Jayaram

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Dissertation Defense Presentation

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  1. Dissertation Defense Presentation Topic:A study of functional architecture of theInternet Protocol-Television (IPTV) and VLSI realization of streaming server controller Committee Members:Presented by: Dr. Subbarao V. Wunnava (Major Advisor) Vivekananda Jayaram Dr. Jean Andrian Date: Nov 13, 2007 Dr. Tadeusz Babij Dr. Shih-Ming Lee

  2. Module Outline • Research Problem • Methodology • IPTV Architecture • Protocols • Audio and Video Compressions • Transmitters and Receivers • VLSI Realization • Results • Contributions • Discussions • Summary

  3. Research Problem • IPTV is fast competing with the broadcast television, and not much information is available; as such to study the scope and maturity of the IPTV in the present times • To investigate the functional architecture of the IPTV system • To design, simulate, and implement a Very Large Scale Integration (VLSI) based system for Streaming Server Controller (SSC), an integral part of the IPTV system

  4. Research Problem Contd.. • To study and investigate different ways of hosting a web server which models the SSC • To implement a functional SSC model on a Field Programmable Gate Array (FPGA) module, which can generate the needed timing and control signals for the IPTV functioning • To scale the VLSI designs for applicability into an ASIC (Application Specific Integrated Circuit) Micro Chip

  5. Research Tasks Performed • Investigated the IPTV configurations in Europe, Asia, and United States, and formulated the common platform for the IPTV architecture • Investigated the appropriate protocols suites which can be used with the IPTV transmission and identified the pros and cons regarding the reliability and security of transmission • Investigated the Computer Communication networking schemes with specific reference to the IPTV • TCP platform Acknowledgement, security • UDP platform Open end, fast • Investigated the VLSI design platforms from the Mentor Graphics and Xilinx corporations, for possible implementation of the IPTV controllers

  6. Research Tasks Performed Contd.. • Investigated the Windows, Linux, and UNIX platforms, with specific requirements of developing the VLSI IPTV –SSC functional system • Investigated different streaming media platforms available and identified the limitations which need to be addressed in the present controller development • Xilinx University Program FPGA board Virtex II Pro XCV2VP30 is used as a target board to implement the streaming server controller module • Web server is hosted on a PowerPC processor embedded in the XCV2VP30 FPGA.

  7. IPTV Architecture

  8. IPTV competitive landscape Successful Industry: Multi vendor participation, multi organizational development, wide end user acceptance

  9. Internet Protocol Suite

  10. TCP/IP Suite • 16-bit unsigned Port Numbers • (1-65535 ) • Well known • Registered • Dynamic/Private • FTP: 21 • SSH: 23 • TELNET: 23 • SMTP: 25 • HTTP : 80 Operates at Layer-4 of OSI model

  11. User Datagram Protocol DNS SNMP DHCP RIP • Small transport layer designed on top of IP • Time-sensitive applications often use UDP • It’s stateless nature is also useful for servers that answer small queries from huge numbers of clients. • It supports packet broadcast (sending to all on local network) and multicasting (send to all subscribers).

  12. UDP in IPV4 Vs IPV6 IPV4 IPV6

  13. TV Content • Live Video • Stored Video (VOD) • Video Broadcast

  14. Analog Broadcast • NTSC - 1941 – 30 Frames/Sec, 525 scan lines per frame, odd (upper) fields drawn first, even (lower) fields later • PAL – 25 Frames/Sec, 625 scan lines per frame

  15. Need for Digital Broadcast • US television stations are scheduled to switch to digital output • In 1996, US Congress had declared December 2006 to be the switchover date • Later extended to February 2009 • From March 2007, all TV’s have Digital or HDTV Tuner

  16. Digital Broadcast • ATSC – Zenith developed 8-VSB (8 way QAM), Digital data stream of about 19.2 Mbit/s, • DVB-T – Coded OFDM, 8000 independent carriers, immunity from multipath interference, data rates from 4 MBit/s up to 24 MBit/s • DVB-S – 1995, MPEG-2, Forward error coding and modulation standard for satellite television , serves every continent, used in direct broadcast satellite services like sky Digital (UK), Astra (Europe), Dish Network (U.S), and Bell ExpressVu (Canada)

  17. Digital Broadcast Contd.. • DVB-C - Cable, DVB European Standard for digital television over cable, transmits an MPEG-2 family digital audio/video stream, using a QAM with channel coding. • ISDB – Japan,Differs mainly in the modulations used, due to the requirements of different frequency bands. • 2 GHz band ISDB-S - PSK modulation • 2.6 GHz band digital sound broadcasting – CDM • ISDB-T (in VHF and/or UHF band) uses COFDM with PSK/QAM.

  18. DTV Advantages • Digital channels take up less bandwidth • Digital broadcasters can provide more digital channels in the same space • Provide High-definition television service, or provide other non-television services such as multimedia or interactivity. • DTV also permits special services such as multiplexing • more than one program on the same channel • electronic program guides • additional languages ( spoken or subtitled )

  19. DTV Disadvantages • DTV picture technology is still in its early stages. • DTV images have some picture defects that are not present on analog television or motion picture cinema, due to present-day limitations of bandwidth and compression algorithms such as MPEG-2. • When a compressed digital image is compared with the original program source, some hard-to-compress image sequences may have digital distortion or degradation. For example: • Quantization noise • Incorrect color • Blockiness • Blurred, shimmering haze

  20. Need for Compression • IP is a digital platform • Analog television when converted into digital format produces continuous stream of digital bits • IPTV service involves heavy amount of transmission of television signals • LAN is capable of 10 to 100 Mbps • HDTV frame of 1920x1080 pixels, computer takes over 2 million operations to read from memory and transfer to video output buffer • Storage, transmission and processing problem

  21. Color depths and Image sizes

  22. Standard Video Compression Formats • AVI – FourCC, M-JPEG, DivX, RIFF, MS • WMV – MS, SMPTE, WMV-9, VC-1, ASF • MPEG-1 – Sampling dimensions (4095 x 4095 x 60) FPS • MPEG-2 – Bit stream, Multiplexed, DVB, FCC Compliant • MEG-4 – Interactive, Virtual Reality, Simulations, Multi viewpoint Training • H.264 – MPEG-4 Part-10, AVC, RTP, 4 hrs Video DVD

  23. IP Content Viewing • Downloading • Streaming • HTTP Streaming • Streaming Server

  24. Streaming Media Platforms Of the several platforms studied and investigated, the following standout: • Helix Universal Server from Real Networks • QuickTime Streaming Server from Apple • Flash Media Server 2 from Macromedia

  25. Live video streaming

  26. Streaming Multicast Streaming Live Video IGMP Unicast Streaming Video On Demand RTSP

  27. UDP streaming Vs TCP/IP streaming • TCP/IP streaming • AVI/ASF • Reliable connection, guarantees packet delivery, Resend packet • Not efficient for live streaming, congested networks • Two-way communication (streaming device  client and client  streaming device). • UDP streaming • Stream live data • No guarantee of packet delivery • Less overhead and better throughput than TCP/IP • Commonly used to send MPEG2 transport data • One-way communication (streaming device  client).

  28. Client Server module

  29. Need for Streaming Server • Extended Storage, Video Compression, Digital Encoders • Buffer Memory • Exchange Servers • Electronics for bit coding • Error Detection & Correction for Video frames

  30. Streaming Server Capabilities • MPEG-2 with DVD level video encoding at 6 Mbps, MPEG-4 with HDV encoding at 10 MBPS • QOS depends on efficiency and fault tolerance • To store 10 sec video = 100Mbps = 12.5MB ; For 100 Channels, buffer size = 1.25 GB • Capability to add the channel numbers and sequence numbers for the packets, fault correction schemes.

  31. VLSI Realization Process Streaming server Controller Determine requirements Write Specifications Synthesis and Verification FPGA Implementation Test development ASIC Specifications MOSISFabrication Manufacturing Test ASICChips

  32. VLSI Design Flow Design Code Simulation Synthesis Floor Planning IC Layout Functional Simulation IC Design Design Rule Check Layout Simulation Padding Scaling to MOSIS

  33. Simulation and Synthesis tools Aldec Altera Cadence Mentor Graphics Quick Logic Symphony Synopsis Synplicity Xilinx

  34. Simulation and Synthesis Tools Picture Courtesy: Mentor Graphics

  35. Xilinx – Virtex II Pro Picture Courtesy: Xilinx Corp.

  36. Xilinx - Virtex II Pro board Picture Courtesy: Xilinx Corp.

  37. Virtex II Pro Features In a single device, we get, • Advanced logic • Performance • Density • Memory • IBM 400 MHz PowerPC™ processors • 622 Mbps to 6.25 Gbps full duplex serial transceivers.

  38. Virtex II Pro Features Contd.. Superior Programmable Logic Architecture • Built on a 130 nm, 9-layer copper process technology • 3K to 99K logic cells • Up to 444 18X18 embedded multipliers • 400+ MHz clock rates • Higher performance and lower power consumption than earlier generation technologies

  39. VHDL……? • VHDL is a language for describing digital electronic systems. • It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. • Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the IEEE in the US.

  40. VHDL Programming

  41. System-on-a-chip (SOC) Controller Transmission Medium DATA Terminal

  42. Block Diagram of webserver system

  43. PowerPC Processor connected to JTAG • Embedded 400 MHz, RISC core • (32-bit Harvard architecture) • 5-stage data path pipeline • Hardware multiply and divide • 32 x 32-bit general-purpose registers • 16 KB 2-way set-associative instruction and data caches • Memory Management Unit (MMU) enables RTOS implementation • Debug and trace support • Timer facilities

  44. JTAG Connectors Depending on the debugging tools, different designs are required in RTL • Using Generic I/O pins to access PowerPC JTAG Debug Ports • Each PowerPC has dedicated I/O pins and a JTAG chain • Select "Single Device" in the SingleStep JTAG and Register settings. • Sharing FPGA JTAG Pins • Connect all PPC JTAG pins into one chain

  45. Memory Unit • 64KB DATA • 64KB INSTRUCTION • 512MB EXTERNAL RAM

  46. Ethernet MAC and Peripheral Blocks • On-Chip Peripheral Bus • Processor Local bus • 10/100 Ethernet MAC • IEEE Std. 802.3 specification • 64-bit PLB master and slave interfaces. • DMA capabilities • Low processor and bus utilization • Media Independent Interface (MII) • For connection to external 10/100 Mbps PHY transceivers • Independent internal TX and RX FIFOs (2K - 32K) • Evaluation version available in EDK

  47. PowerPC Architecture

  48. Implementation: Configuring PowerPC

  49. Implementation: Configuring Data Path

  50. Implementation: Xilinx Platform Studio

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