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Clockless Logic

Clockless Logic. Review Logic Implementation Styles: Static CMOS logic Dynamic logic, or “domino” logic Transmission gates, or “pass-transistor” logic. Static CMOS logic. Advantages: output always strongly driven

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Clockless Logic

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  1. Clockless Logic Review Logic Implementation Styles: Static CMOS logic Dynamic logic, or “domino” logic Transmission gates, or “pass-transistor” logic

  2. Static CMOS logic Advantages: • output always strongly driven • pull-up and pull-down networks are fully-complementary;exactly one of them is “on” always • good immunity from noise and leakage • both inverting and non-inverting functions implementable • each gate is inverting • cascade two gates together to get non-inverting logic Disadvantages: • slow/big PMOS devices needed (in addition to NMOS) • greater chip area • higher power consumption • slower switching speed

  3. Dynamic Logic, or “domino” Key idea: • only use NMOS’s to compute function • use a single PMOS to reset Advantages: • significantly fewer transistors  smaller chip area • higher speed, lower power • less “loading” on wires (drive fewer transistors) • for async: no storage elements needed Disadvantages: • need extra control input to precharge • logic is typically non-inverting only • more vulnerable to noise and leakage effects

  4. Dynamic Logic, or “domino” (contd.) Gate has 2 phases: • precharge (=reset): output reset to ‘0’ • evaluate: output computed  either stays ‘0’, or switches to ‘1’ Pull-up and pull-down must never both be simultaneously active: • ensure that data inputs are reset while gate is precharging • or, add a “footer” device control input controls“precharge” PC PC =0 (asserted)  precharge pull-upnetwork pull-down network dataoutput PC =1 (de-asserted)  evaluate datainputs controls“evaluation”

  5. Transmission Gates Key Idea: • transistors used in a different configuration • when switched on: instead of connecting output to Vdd or Gnd, they connect output to the input Advantage: • very efficient for implementing switches and multiplexors Disadvantage: • not very useful for logic functions

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