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CS/EE 3700 : Fundamentals of Digital System Design

CS/EE 3700 : Fundamentals of Digital System Design. Chris J. Myers Lecture 5: Arithmetic Circuits Chapter 5 (minus 5.3.4). Positional Number Representation. Decimal: D = d n-1 d n-2 ...d 1 d 0 V(D) = d n-1  10 n-1 + d n-2  10 n-2 + ... + d 1  10 1 + d 0  10 0 Binary:

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CS/EE 3700 : Fundamentals of Digital System Design

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  1. CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 5: Arithmetic Circuits Chapter 5 (minus 5.3.4)

  2. Positional Number Representation • Decimal: • D = dn-1dn-2...d1d0 • V(D) = dn-1 10n-1 + d n-2 10n-2 + ... + d1 101 + d0 100 • Binary: • B = bn-1bn-2...b1b0 • V(B) = bn-1 2n-1 + b n-2 2n-2 + ... + b1 21 + b0 20 (5.1)

  3. Conversion: Binary to/from Decimal • Conversion of binary to decimal: use 5.1. • (1101)2 = • Conversion of decimal to binary: • V = bn-1 2n-1 + b n-2 2n-2 + ... + b1 21 + b0 • V/2 = bn-1 2n-2 + b n-2 2n-3 + ... + b1 + b0/2 • Quotient is: bn-1 2n-2 + b n-2 2n-3 + ... + b1 • Remainder is: b0 • If remainder is 0 then b0 = 0, if it is 1 then b0 = 1. • Repeat on quotient to find b1, etc.

  4. Convert (857)10 to binary: Figure 5.1 Conversion from decimal to binary

  5. Table 5.1 Numbers in different systems

  6. Conversion: Binary to Oct or Hex • (101011010111)2 • (10111011)2 • (1010111100100101)2 • (1101101000)2

  7. Addition of Unsigned Numbers x + y ---- c s sum carry

  8. Addition of Unsigned Numbers x y c s

  9. (15)10 (10)10 Figure 5.3 An example of addition

  10. Figure 5.4 Full-adder

  11. Use of XOR Gates

  12. Circuit for Full Adder

  13. s c s i i HA c s x i c HA c i + 1 y i (a) Block diagram c i s i x i y i c i + 1 (b) Detailed diagram Figure 5.5 A decomposed implementation of the full-adder circuit

  14. x y x y x y 1 1 0 0 n – 1 n – 1 c 1 c c c c FA FA FA n ” 1 n 0 2 s s s n – 1 1 0 MSB position LSB position Figure 5.6 An n-bit ripple-carry adder

  15. A : a a 7 0 x x y y 7 0 7 0 c 7 s s 7 0 0 x x x y y y 8 7 0 8 7 0 c 8 s s 8 0 : P = 3 A P P P 9 8 0 (a) Naive approach Figure5.7 Circuit that multiplies an 8-bit unsigned number by 3

  16. A : a a 7 0 0 0 x x x y y y 8 1 0 8 7 0 c 8 s s 8 0 : P = 3 A P P P 9 8 0 (b) Efficient design Figure5.7 Circuit that multiplies an 8-bit unsigned number by 3

  17. b b b n – 1 1 0 Magnitude MSB (a) Unsigned number b b b b n – 2 n – 1 1 0 Magnitude Sign 0 denotes + – MSB 1 denotes (b) Signed number

  18. Sign Magnitude • Magnitude of positive and negative numbers represented in same way. • Sign used to distinguish them. • Simple to understand. • Complicates hardware design.

  19. 1’s Complement • n-bit negative number found by subtracting its positive form from 2n-1. • K1 = (2n – 1) – P • Found by just complementing each bit. • Examples:

  20. 2’s Complement • n-bit negative number found by subtracting its positive form from 2n. • K2 = 2n – P • K2 = K1 + 1 • Complement each bit and add 1. • Examples:

  21. Sign Magnitude: Add/Sub • If both operands have the same sign, then addition is simple. • Add magnitudes and copy the sign. • If they have opposite sign, then must subtract smaller from the larger. • This is complicated, so sign magnitude not typically used in computers.

  22. ( – 5 ) ( ) + 5 ( ) ( ) + + 2 + + 2 ( ) ( - 3 ) + 7 ( ) + 5 ( – 5 ) + ( – 2 ) + ( – 2 ) ( ) ( – 7 ) + 3 Figure 5.9 Examples of 1’s complement addition

  23. ( – 5 ) ( ) + 5 ( ) ( ) + + 2 + + 2 ( ) ( - 3 ) + 7 ( ) + 5 ( – 5 ) + ( – 2 ) + ( – 2 ) ( ) ( – 7 ) + 3 Figure 5.10 Examples of 2’s complement addition

  24. ( ) + 5 ( ) – + 2 ( ) + 7 ( ) + 5 – ( – 2 ) ( ) + 3 Figure 5.11 Examples of 2’s complement subtraction

  25. ( – 5 ) ( ) – + 2 ( - 3 ) ( – 5 ) – ( – 2 ) ( – 7 ) Figure 5.11 Examples of 2’s complement subtraction

  26. 0000 1111 0001 1110 0010 0 – 1 + 1 – 2 + 2 1101 0011 – 3 + 3 – 4 + 4 1100 0100 – 5 + 5 1011 0101 – 6 + 6 – 7 + 7 – 8 1010 0110 1001 0111 1000 Figure 5.12 Graphical interpretation of four-bit 2’s complement numbers

  27. y y y n – 1 1 0 ¤ Add Sub control x x x n – 1 1 0 c c n -bit adder 0 n s s s n – 1 1 0 Figure 5.13 Adder/subtractor unit

  28. ( ) ( ) + 7 – 7 ( ) ( ) + 2 + 2 + + ( ) – 5 ( ) + 9 ( ) ( ) + 7 – 7 ( ) ( ) + + – 2 – 2 ( ) – 9 ( ) + 5 Figure 5.14 Examples of determination of overflow

  29. Detecting Overflow • Overflow = c3c4’ + c3’c4 = c3 c4 • For n-bit numbers, • Overflow = cn-1  cn

  30. Performance Issues • Price/performance ratio is important. • Speed of addition/subtraction has impact on overall speed of a microprocessor. • Worst-case delay of a ripple carry adder is: • n  t • Assume  t = 2 gate delays and xor = 1. • Total delay = 2n + 1 gate delays. • Must reduce critical path delay.

  31. Carry-Lookahead Adder • Must determine carry quickly. • ci+1 = xiyi + xici + yici • ci+1 = xiyi + (xi + yi)ci • ci+1 = gi+ pici where gi = xiyi (generate) pi = xi + yi (propagate) • ci+1 = gi+ pi (gi-1+ pi-1ci-1) • ci+1 = gi+ pigi-1+ pipi-1ci-1 • ci+1 = gi+ pigi-1+ pipi-1gi-2 + ...+pipi-1...p1g0 + pipi-1...p0c0

  32. x y x y 1 1 0 0 g p g p 1 1 0 0 c 1 c c 0 2 Stage 1 Stage 0 s s 1 0 Figure 5.15 A ripple-carry adder with generate/propagate signals

  33. x y x y 1 1 0 0 x y 0 0 g p g p 1 1 0 0 c 0 c 2 c 1 s s 1 0 Figure 5.16 The first two stages of a carry-lookahead adder

  34. High Fan-in Issues • c1 = g0+ p0c0 • c2 = g1+ p1g0+ p1p0c0 • ... • c8 = g7+ p7g6+ p7p6g5 +p7p6p5g4 +p7p6p5p4g3 +p7p6p5p4p3g2 +p7p6p5p4p3p2g1 +p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0 • c8 = (g7+ p7g6+ p7p6g5 +p7p6p5g4) + [(p7p6p5p4)(g3 + p3g2 +p3p2g1 +p3p2p1g0)+ (p7p6p5p4)(p3p2p1p0)c0

  35. x y x y x y 15 – 8 15 – 8 7 – 0 7 – 0 31 – 24 31 – 24 c 8 Block Block Block c c c c 32 24 16 0 3 1 0 s s s 31 – 24 15 – 8 7 – 0 Figure 5.17 A hierarchical carry-lookahead adder with ripple-carry between blocks

  36. Group Propagate/Generate • c8 = g7+ p7g6+ p7p6g5 +p7p6p5g4 +p7p6p5p4g3 +p7p6p5p4p3g2 +p7p6p5p4p3p2g1 +p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0 • P0 = p7p6p5p4p3p2p1p0 • G0 = g7+ p7g6+ ...+p7p6p5p4p3p2p1g0 • c8 = G0 + P0c0 • c16 = G1 + P1G0 + P1P0c0 • c24 = G2 + P2G1 + P2P1G0 + P2P1P0c0 • c32 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

  37. x y x y x y 31 – 24 31 – 24 15 – 8 15 – 8 7 – 0 7 – 0 Block Block Block c 0 3 1 0 c 24 G P G P G P 3 3 1 1 0 0 s s s 31 – 24 15 – 8 7 – 0 c c c 32 16 8 Second-level lookahead Figure 5.18 A hierarchical carry-lookahead adder

  38. x y x y 1 1 0 0 g p g p 1 1 0 0 c 0 c 2 c 1 s s 1 0 Figure 5.19 An alternative design for a carry-lookahead adder

  39. Figure 5.20 Schematic using an LPM adder/subtractor module

  40. Optimized for cost Optimized for speed Figure 5.21 Simulation results for the LPM adder

  41. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY fulladd IS PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END fulladd ; ARCHITECTURE LogicFunc OF fulladd IS BEGIN s <= x XOR y XOR Cin ; Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ; END LogicFunc ; Figure 5.23 VHDL code for the full-adder

  42. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ; Figure 5.24 VHDL code for a four-bit adder

  43. LIBRARY ieee ; USE ieee.std_logic_1164.all ; PACKAGE fulladd_package IS COMPONENT fulladd PORT ( Cin, x, y : IN STD_LOGIC ; s, Cout : OUT STD_LOGIC ) ; END COMPONENT ; END fulladd_package ; Figure 5.25 Declaration of a package

  44. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; x3, x2, x1, x0 : IN STD_LOGIC ; y3, y2, y1, y0 : IN STD_LOGIC ; s3, s2, s1, s0 : OUT STD_LOGIC ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL c1, c2, c3 : STD_LOGIC ; BEGIN stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ; stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ; stage3: fulladd PORT MAP ( Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; END Structure ; Figure 5.26 Using a package for the four-bit adder

  45. STD_LOGIC_VECTOR’s • SIGNAL C : STD_LOGIC_VECTOR(1 TO 3); • C <= “100” equivalent to: • C(1) = ‘1’, C(2) = ‘0’, C(3) = ‘0’ • SIGNAL X : STD_LOGIC_VECTOR(3 DOWNTO 0); • X <= “1100” equivalent to: • X(3) = ‘1’, X(2) = ‘1’, X(1) = ‘0’, X(0) = ‘0’

  46. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE work.fulladd_package.all ; ENTITY adder4 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ; Cout : OUT STD_LOGIC ) ; END adder4 ; ARCHITECTURE Structure OF adder4 IS SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ; BEGIN stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ; stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ; stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ; stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ; END Structure ; Figure 5.27 A four-bit adder defined using multibit signals

  47. Arithmetic Packages • std_logic_signed package defines signed arithmetic for std_logic type. • std_logic_unsigned package defines unsigned arithmetic for std_logic type. • These are built on top of the package std_logic_arith.

  48. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS BEGIN S <= X + Y ; END Behavior ; Figure 5.28 VHDL code for a 16-bit adder

  49. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_signed.all ; ENTITY adder16 IS PORT ( Cin : IN STD_LOGIC ; X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ; S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ; Cout, Overflow : OUT STD_LOGIC ) ; END adder16 ; ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ; BEGIN Sum <= ('0' & X) + Y + Cin ; S <= Sum(15 DOWNTO 0) ; Cout <= Sum(16) ; Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ; END Behavior ; Figure 5.29 A 16-bit adder with carry and overflow

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