Fundamentals of Digital Engineering:. Digital Logic A MicroCourse. R. Katz Grunt Engineer Design Engineer (retired) May 21, 2001. Abstract.
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Fundamentals of Digital Engineering:
Digital Logic
A MicroCourse
R. Katz
Grunt Engineer
Design Engineer (retired)
May 21, 2001
The basics of Boolean algebra will be introduced, starting from simple combinational logic functions and basic sequential logic circuits such as latches and flipflops. Based on these fundamentals, more complex logic structures such as decoders, adders, registers, and memories will constructed and their performance analyzed. FET Transistor basics will be reviewed and circuits introduced that demonstrate implementations of the basic logic elements in CMOS technology. The logic functions used as the architectural basis for programmable devices used in spaceborne electronics will be examined and analyzed.
Some common design problems found in flight circuits will be introduced.
2.0 V
0.8 V
0.8 V < v < 2.0 V
Logic ‘1’
2.0V
Undefined
0.8V
Logic ‘0’
> +VTH
<  VTH
VTH < v < +VTH
1http://www.intel.com/design/flcomp/prodbref/298044.htm
Logic Values and Basic Functions
TYPE std_ulogic IS (
‘U’,  Uninitialized
‘X’,  Forcing Unknown
‘0’,  Forcing 0
‘1’,  Forcing 1
‘Z’,  High Impedance
‘W’,  Weak Unknown
‘L’,  Weak ‘0’
‘H’,  Weak ‘1’
‘’  Don’t Care
);
A Y
0 1
1 0
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Inputs AND gates OR gates Inverters Outputs
Universal Logic Element
Y = ( A + B )´
Y = ( A • B )´
Y = A • S + B • S´
Small memory
Y = ( A + B )´
NOT
AND
OR
Y = ( A • B )´
NOT
AND
OR
Y = A • S + B • S´
OR
AND
NOT
Small memory
NOT OR AND
A X Y A B Y A B Y
0 0 1 0 0 0 0 0 0
0 1 1 0 1 1 0 1 0
1 0 0 1 0 1 1 0 0
1 1 0 1 1 1 1 1 1
Logic Assignments and Duality
Logic Gate  Positive Logic
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
0 = 0V
1 = 5V
Logic Gate and Voltage
A B Y
0V 0V 0V
0V 5V 0V
5V 0V 0V
5V 5V 5V
Logic Gate  Negative Logic
A B Y
1 1 1
1 0 1
0 1 1
0 0 0
1 = 0V
0 = 5V
Logic Gate  Negative Logic
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
1 = 0V
0 = 5V
Reorder Rows
Adders
Truth Table
x y C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Logic Equations
C = x • y
S = x y
Schematic
Truth Table
x y z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Logic Equations
C = x’yz + xy’z + xyz’ + xyz
= z • (x’y+xy’) + xy • (z+z’)
= z • (x y) + x • y
= MAJ (x,y,z)
S = x’y’z + x’yz’ + xy’z’ + xyz
= x’yz’ + xy’z’ + x’y’z + xyz
= z’(x’y + xy’) + z(x’y’ + xy)
= z’(x y) + z(x y)’
= (x y) z
= x y z
Transistors
drain
collector
body
base
gate
source
emitter
npn bipolar transistor
nchannel MOSFET
collector
collector
base
base
emitter
emitter
pnp bipolar transistor
npn bipolar transistor
A circle is sometimes
used on the gate terminal
to show active low input
Basic MOSFET
Show how MOSFET can be used as a switch
VDD
p
A
Y = A'
n
GND
Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.
When input A is grounded (logic 0), the Nchannel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the Pchannel MOSFET is forward biased, so it has a channel enhanced within itself, connecting the output line to the +Vsupply. This pulls the output up to +V (logic 1).
When input A is at +V (logic 1), the Pchannel MOSFET is off and the Nchannel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pullup and pulldown, according to the output state.
This basic CMOS inverter can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. A practical example of a CMOS 2input NOR gate is shown in the figure.
In this circuit, if both inputs are low, both Pchannel MOSFETs will be turned on, thus providing a connection to +V. Both Nchannel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that Pchannel MOSFET will turn off and disconnect the output from +V, while that Nchannel MOSFET will turn on, thus grounding the output.
Note the two pchannel FETs in series.
A twoinput NAND gate: a logic 0 at either input will force the output to logic 1; both inputs at logic 1 will force the output to go to logic 0.
Note the two nchannel FETs in series and the two pchannel FETs in parallel.
The pullup and pulldown resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or Bseries CMOS gates.
The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either Pchannel or Nchannel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Typically, the pchannel transistor is approximately twice as wide as the nchannel transistor, because of the difference in conductivity between electronics and holes.
Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here. This is not strictly true for most CMOS devices for applications that are powerswitched; special inputs are required for poweroff isolation between circuits.
Decoders
Binary
Decimal Unencoded Encoded
0 0001 00
1 0010 01
2 0100 10
3 1000 11
Note: Finite state machines may be unencoded ("onehot")
or binary encoded. If the all 0's state is used, then
one less bit is needed and it is called modified
onehot coding.
1 1
1 0
0 1
00
What happens when the inputs goes from 01 to 10?
1 1
1 0
0 1
00
2:1 Mux implemented by
minimized SumofProducts
Idealized matched delays
In real circuits, delays don't
exactly match; Added delay
for illustration
We now have a "glitch."
Same waveform, zoomed in.
A B
1 1
1 0
0 1
0 0
0
1
1
0
S=0
S=1
1
0
1
0
Illustrating the minimized function on a Karnaugh map.
Only two 2input AND gates are needed for the product terms
A B
1 1
1 0
0 1
0 0
0
1
1
0
S=0
S=1
1
0
1
0
The blue oval shows the redundant term used to cover the
transition between product terms.
How can we verify the
presence and operation
of the ‘redundant’ gate?
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
1000 8
1001 9
1010 10
1011 11
1100 12
1101 13
1110 14
1111 15
0000 16
Terminal count of
a 4bit synchronous
counter.
TMR Triplet Majority Voter
Highskew buffer
Care is needed when using TMR circuits. First, the output of the voter may be susceptible to a logic hazard “glitch.” This is not a problem if the TMR is feeding the input of another synchronous input. However, the TMR output should never feed asynchronous inputs such as flipflop clocks, clears, sets, read/write inputs, etc.
“Design Techniques for RadiationHardened FPGAs”
Actel Corporation, September 1997
 based on “SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space
Applications and Device Characterization,” R. Katz, R. Barto, et. al., IEEE Transactions
on Nuclear Science, Dec. 1994.
We have covered static hazards. There are also dynamic hazards. An example of a dynamic hazard would be when a circuit is supposed to switch as follows:
0 1
But instead switches:
0 1 0 1
Any circuit that is static hazard free is also dynamic hazard free.
VCC
Output Stage
+
Programmable
Load
i

VCC
Output Stage
+
VCC
Programmable
Load
i

A1460A TID (VOL) TestPostIrradiation
RT54SX32 TID (VOH) TestPostIrradiation
RT54SX32 TID (VOL) TestPostIrradiation
FlipFlops
A flipflop holds 1 "bit".
"Bit" ::= "binary digit."
The present state is held when CP is low.
Negative Pulse
Positive Pulse
Positive
Edge
Negative
Edge
Negative
Edge
Positive
Edge
Edges can also be referred to as leading and trailing.
Master Slave
Worstcase Military Conditions, VCCA=2.3, VCCI=3.0V, TJ=125C
1 Speed Grade
Min Max Units
tRCO Sequential ClocktoQ 1.0 ns
tCLR Asynchronous CleartoQ 0.9 ns
tPRESET Asynchronous PresettoQ 1.0 ns
tSUD FlipFlop Data Input SetUp 0.6 ns
tHD FlipFlop Data Input Hold 0.0 ns
tWASYN Asynchronous Pulse Width 1.8 ns
Metastability  Introduction
Metastability
Metastability  Calculation
t is the slack time available for settling
K1 and K2 are constants that are characteristic of the flipflop
Fclock and Fdata are the frequency of the synchronizing clock and asynchronous data.
Metastability  Sample Data
Synchronizer (Bad Circuit)
Correct Output
Parallel Registers
Register 2
Q
D
Register 1
CLK
Address  log2(num registers)
D and Q are both sets of lines, with the number of lines
equal to the width of each register. There are often multiple
address ports, as well as additional data ports.
Decoder
(AND plane)
MagneticCoreMemory
Register
Sense wires serve as OR plane.
SemiconductorMemory
Decoder
(AND plane)
OR plane
RadHard PROM Architecture
No latches in this architecture
E2
Memory
Array
Edge
Detect &
Latches
Row
AddressDecoder
Column
AddressDecoder
Row
AddressLatches
Column
AddressLatches
64 Byte
Page
Buffer
Control
Latch
Control
Logic
Timer
I/O Buffer/
Data Polling
A612
A05
CE*
WE*
Latch Enable
OE*
CLK
VW
I/O07
PE
RSTB
Module Design of PALs and FPGAs
AND
Plane
OR
Plane
FlipFlops (optional)
Inputs + Buffers/Inverters
Inverters + Outputs
PROMs, PALs, and PLAs all have a similar architecture
Programmable AND plane and
fixed OR plane.
PALs have a builtin POR circuit to initialize all registers to zero.
8Input Combinational function
766 possible combinational
macros1
1”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal,
Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp. 10421056
Act 2 Flipflop Implementation
Feedback goes through
antifuses (R) and routing
segments (C)
Hardwired Flipflop
Routed or “CC Flipflop”
RE
WA(8:0)
WD(17:0)
RCLK
RA(8:0)
WE
WCLK
RD(17:0)
ASYNCRD
MODE(1:0)
RAM LUTs
for Logic or
small SRAM
Two Flipflops
Placement is important for performance.
General interconnect
Effective Carry Logic for a Typical Addition  XQR4000XL
MRC Orion Logic Module
28 unique functions