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Fast, efficient and scalable multi-corner SoC Signoff analysis extension with programmable in-situ Spice level analysis capability. ST MICROELECTRONICS.

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slide1

Fast, efficient and scalable multi-corner SoC Signoff analysis extension with programmable in-situ Spice level analysis capability

ST MICROELECTRONICS

Anjali Supekar *, Mohita Batra *, Rakesh Gulati *, Shahabuddin Qureshi °, Hina Mushir#, Prashant Pandey#, Samant Paul °, Seema Jaiswal °

* Automation Team ° IP Team # Silicon Test and Debug Team

slide2

Due to reduced margins in the SOC design, number of critical path are increasing.

  • Digital timing analysis methods are shaking hands with spice validation methodologies resulting in mixed signal analysis modes.
  • CURRENT METHODS:
  • Highly time consuming
  • Use complete spice (large size)

However…..

  • OUR INTEND:
  • Simulating any path of any hierarchy of a design
  • Quick & flexible analysis of true behavior of the path over wide range of operating conditions
  • Use output of the tool to optimize the design .
slide3

STA

Mixed Mode

Multiple corner butTime Taking

Limited corner

Huge pattern set

Less Accurate

Unable to characterize small portion of hard IP

Large coverage(Not specific, unsuitable for flat design)

With change in technologies, there was a need to reduce the “extra margin” under consideration in order to get characterization for a small area leading to more optimistic approach. With the existing options (Sign Off /Mixed Mode) , analysis was possible only at full block level and hierarchical analysis was not supported. For such huge hierarchies we have developed a solution which lies between HDL and mixed mode analysis . The solution provides extraction at multiple corners and increased accuracy

slide4

APPLICATION UNDER STUDY: CAD CORRECTION FACTOR

Q Slope

Clock Slope

  • Expected Access Time on Silicon: TA
  • Actual Access Time obtained from CAD: TAA
  • CAD Correction Factor (CCF) Δ = TA - TAA
  • TA =Δ + TAA

Source Clock

Memory

Q1

LSB

1

Load

Clock

  • Total Contribution (4-1)
  • Balancing Contribution (2-1)
  • Path Contribution ( 4-3)
  • PulseGen Contribution (3-2)

Q2

MSB

4

2

3

Pulse Generator

Sensor

Pulse Clock

Pulse Propagation

CK & Q

PULSE FROM

MEM

CCF

slide5

PROBLEM STATEMENT:

  • The TAAmeasured on chip measurement (Sensor) is going below CAD fast limits.
  • CAD analysis on TAApulse propagation from memory to Sensor shows reduction in pulse width

Test chip logic for pulse propagation

And mixing to a central location

Central

Location

(Pulse

To digital

Conversion)

CUT1

Memory

Q

PULSEGEN

(Sensor lib)

CK

Sensor

-Balanced structure

(Controlled placement and routing etc)

CUTn

Memory

Digital

Output

Q

PULSEGEN

(Sensor lib)

CK

Pulse variation Error depends on input Slopes.

Error of the order of medium size inverter delay

Error sources in

TAAmeasurement

TERROR-TC : Rise (Edge) Delay – Fall (Edge) Delay

This value (extracted from STA) is provided in testdoc on signoff conditions for each cut

slide6

CCF TOOL FLOW

SimulationEnvironment

LoadSlopes XLS

Clock Slopes XLS

Spice Simulator

Detailed CCF

slide7

The PVT Generator is an automation tool written in VB which facilitates the generation of PVT sheet from the standard input sources from the Front End and Sensor data

INPUTS

  • Memory Test Specification
  • Clock SlopeDelivered along with SPICE files
  • PVT Mapping Information
    • Simulation and Spice Extraction Temperature
    • Process and RC Extraction
slide9

CCF Flow involves parsing of PVT Topsheet which contains CUT details and PVT information for CCF calculations.

  • For Spice simulation, it processes Spice to be directly used, write simulation stubs for each cut, to calculate Clock slopes and CCF.
  • Simulation Environment : Automation supports, Writing simulation files and invoking Simulation Environment for launching of clock slope simulations and CCF simulations.
  • Flow supports Compilation of the Clock slopes and CCF for all the CUTs in tool internal format
slide10
Manual (Before Automation)

After Automation

User need not be aware of any simulation tools. Tool is user friendly and no prior knowledge required.

Set-up Time reduced to half an

hour

Parallel simulation along with tracking mechanism. At any point user can check simulation status of any CUT. Simulation time reduced to 4-5 hours

Result compilation made easy with proper monitoring of all sheets for each cut. Time reduced to 5-6 minutes

Easy Debug options

  • Thorough knowledge about Spice files, its extraction, modification, Eldo simulation and other tools for calculating CCF
  • Set-up Time was approximately 1-2 days (includes spice extraction, correction, run files, stimuli and other data files)
  • Simulation was initially sequential. Even if it was parallel, there was no tracking mechanism. Simulation time was approximately 4-5 days
  • Result compilation was tedious as there were many excel sheets having huge data which was unmanageable. It took approximately 8-10 hours
  • No debug options

90% of user time is saved

slide11

CAD CORRECTION FACTOR

T1

T2

T3

T4

T5

SYSTEM ACCURACY

PURE MEMORY CAD

V5 > V1 T5<T1

NEW MEMORY CAD

CAD v/s Silicon Analysis of a Testchip

V1 V2 V3 V4 V5

CAD v/s SI Aligned with

Increased Accuracy of

new CCF

slide12

MOTIVATION

ENHANCEMENTS

PotentialApplications

Proposed solution addresses different components of SOC.

  • Process Sensor Block (for Sensor Data Analysis)
  • Temperature sensitivity
  • voltage sensitivity
  • RC Impact
  • Impact of device sensitivity

CAD Correction Factor (CCF) + MCF (Memory)

A TAA error value calculation for test chips is an important step to calculate path contribution to extract the deviation of CAD from Silicon.

Testchip

Process Sensor

Memory

Ring Oscillators

  • Standard Cell RO Block CAD Data
  • Generation for any type of architecture (flops, mux, etc)
  • easy analysis (currents, timing , frequency)
slide13

EXISTING FLOWNEW OPTIMIZED FLOW

Clock Slope / load @ multiple corners

  • AUTOMATIC CAD CORRECTION FACTOR GENERATION THROUGH MCF

Extract Load slopes @ multiple corners

Clock Slope and Q load @ multiple corners

Extract memory CAD

Extract slope @ multiple corners

simulations for Unified CAD Data {CCF included}

TESTCHIP TEAM

manual adjustment for CCF

Extracts CCF @ multiple corners

CAD Data Delivery

Memory team do delivery of CAD Data to Test team

TESTCHIP TEAM

MEMORY TEAM

3X Gain

MEMORY TEAM

Cycle time + No. of simulations

13

" Faster & Accurate" CAD data generation for Improving Accuracy for CAD vs Si analysis.

slide14

Process Sensor Block

Tool fully automates the Sensor Design Analysis and CAD Data Generation for Silicon validation.

Voltage Sensitivity

Sensor Data Analysis

RC Impact

Temperature Sensitivity

slide15

Enable this tool for SoC designers at physical implementation stage.

  • Option for generating GDS and CDL of a specific portion of targeted block of SOC taking DEF as input and then extracting Spice from GDS and CDL.
  • Analyzing Critical paths using Actual Spice Simulations
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