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Replacement GCT to GT link Greg Iles & Anton Taurok

Replacement GCT to GT link Greg Iles & Anton Taurok. 4 th February 2008. Current System. Legacy of previous GCT design Electrons/Jets/Energy: 14 channels @ 1.6Gb/s Quiet bits: 24 channels @ 1.6Gb/s DC coupled links based on National Semiconductor DS92LV16

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Replacement GCT to GT link Greg Iles & Anton Taurok

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  1. Replacement GCT to GT linkGreg Iles & Anton Taurok 4th February 2008 GTI Status: Greg Iles (gregory.iles@cern.ch)

  2. Current System • Legacy of previous GCT design • Electrons/Jets/Energy: 14 channels @ 1.6Gb/s • Quiet bits: 24 channels @ 1.6Gb/s • DC coupled links based on National Semiconductor DS92LV16 • Advantage of being simple and low latency • However operated at extreme limit of specification • Not ideal • Link loopback errors seen by both GT and GCT groups. • No simple fix GTI Status: Greg Iles (gregory.iles@cern.ch)

  3. New Design • Decouple link from surrounding electronics infrastructure • Use PMC (PCI Mezzanine Card) card • Single card for both transmit and receive • Very little overhead to make card bidirectional • Keep simple • 1 Xilinx Virtex 5 to provide serdes interface • 2 POP4s to provide elec/opto conversion POP4 /4 PMC Header Xilinx V5 /128+40 1.6 Gb/s (data) 80MHz POP4 /4 GTI Status: Greg Iles (gregory.iles@cern.ch)

  4. Old versus New system Src Cards Src Cards 234 @ 1.6 Gb/s 18 @ 1.6 Gb/s 234 @ 1.6 Gb/s 18 @ 1.6 Gb/s VME system for Electrons, Jets uTCA system for Quiet bits VME system for Electrons, Jets uTCA system for Quiet bits 8 x Leaf 2 x Wheel 1 x Concentrator 3 x Matrix 8 x Leaf 2 x Wheel 1 x Concentrator 3 x Matrix 1 x GTI 3 x Converter 2 x OptoGTIs 3 x Converter 14 @ 1.6 Gb/s 24 @ 1.6 Gb/s 14 @ 2.4Gb/s 24 @ 2.4Gb/s 5 PSBs 5 New PSBs each with an OptoGTI All fibre links 850nm, MultiMode GTI Status: Greg Iles (gregory.iles@cern.ch)

  5. Technology choice (I) • Xilinx Virtex 5, XC5VLX30T-FF665 • 3rd generation Xilinx serial link – 3.75 Gb/s • Can run at higher speed to reduce latency. • 8 links per FPGA • Use medium size package to make routing simpler • Simpler PCB layout compared to discrete serdes • Main components top side only • Baseline to run links at 2.4Gb/s (64% max spec) • Flexibily of FPGA behind serdes useful. GTI Status: Greg Iles (gregory.iles@cern.ch)

  6. POP4 fibre optic transceiver Transceiver: 4 in, 4 out Same physical form as SNAP12 on Leaf 850 nm multimode, 1 to 3.125 Gb/s Height OK for VME card 16mm Baseline to run links at 2.4Gb/s 77% max spec Two suppliers AvagoTech: HFBR-7934Z Zarlink: ZL60304 Technology choice (II) GTI Status: Greg Iles (gregory.iles@cern.ch)

  7. Clocking 2 x Micro Coax for neighbour PMC card FPGA PMC Header Clk Buffer PLL Optio Dual LVDS inputs X-point switch x2 Micro Coax PMC Header Clk Buffer PLL Optio Dual LVDS inputs RefClks for POP4-A 2 x Buf Micro Coax x2 Osc A RefClks for POP4-A 2 x Buf x2 Osc B GTI Status: Greg Iles (gregory.iles@cern.ch)

  8. Latency Notes: (a) Latency calculated from clk edge sampling data into SerDes/FPGA until FPGA fabric (b) The numbers are obtained from datasheets and theoretical performace. (c) Assumed 1.0 bx here, but could be 2.0 depending on sync method. (d) No elastic buffer. Tx = 9.5 x RXUSRCLK, Rx = 10.5 RXUSRCLK (e) Assumed ¼ bx for IOB + 2 link speed clks (4 x ½). Based on current 80MHz to 100MHz bridge. (f) All numbers worst case, but no contingency. (g) block ram performance dependent. GTI Status: Greg Iles (gregory.iles@cern.ch)

  9. Advantages of new sys: Links are decoupled from main GCT/GT hardware. New PSB design can run in parallel. Small V5/POP4 board is not a large investment. Relatively quick to design and layout. No uTCA card needed to interface quiet bits to GT. Design still only provsional. To be reviewed by Matt Stettler (GCT Hardware Chief) on his return from the states (Mid Feb) Schedule Reserved layout time from March 1st Unless we confirm that we want to start date soon we may lose this date . Layout will take ~ 6 months due to other commitemnets. Manufacture ~ 1 month. Boards back Oct 1st. Aim to have new link by end of 2008. Conclusions & Schedule GTI Status: Greg Iles (gregory.iles@cern.ch)

  10. End GTI Status: Greg Iles (gregory.iles@cern.ch)

  11. Simulation of 2.4Gb/s link GTI Status: Greg Iles (gregory.iles@cern.ch)

  12. POP4 Xilinx V5 Header POP4 OptoGti-PMC POP4 Xilinx V5 PSB 1 Header POP4 OptoGti-PMC Concentrator Card POP4 POP4 Xilinx V5 Xilinx V5 PSB 2 Header Header POP4 POP4 OptoGti-PMC OptoGti-PMC POP4 Xilinx V5 PSB 3 Header POP4 OptoGti-PMC uTCA system for Quiet bits POP4 Xilinx V5 PSB 4 Header POP4 OptoGti-PMC POP4 Xilinx V5 PSB 5 Header POP4 OptoGti-PMC

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