FEASIBILITY STUDY OF THE DISCRIMINATOR CELL OF EUSO Front End ASIC

1. FEASIBILITY STUDY OF THE DISCRIMINATOR CELL OF EUSO Front End ASIC LABEN S.p.A. 1st Workshop on EUSO Electronics Genova - 5/6 March 2001 A FINMECCANICA COMPANY

2. AGENDA • ASIC ARCHITECTURE DESCRIPTION • OBJECTIVES OF THE STUDY • TECHNOLOGY SELECTION CRITERIA • TECHNOLOGY SURVEY RESULTS • DISCRIMINATOR DESIGN • SUMMARY & OPEN POINTS • TECHNOLOGY STATUS • DEVICE QUALIFICATION FLOW • THINGS TO BE DONE A FINMECCANICA COMPANY

3. ASIC ARCHITECTURE • Front End Asic basic functions : • to pre-amplify and adapt the analogue detector (MAPMT) signal; • to discriminate the detector signals with programmable threshold; • to count the hits of each channel within a fixed time window; • to split the logic signals for the X and Y positions and for the macrocell timing channel. A FINMECCANICA COMPANY

4. ASIC ARCHITECTURE • 8/16/64 (TBD) acquisition channels connected to the anodes of a MA-PMT. • Each channel includes: • Pre-Amplifier stage. • High speed comparator to: • discriminate single photoelectron anodic pulses • double pulse resolution of 10 ns for subsequent pulses • Digital counter : • 3-bits programmable threshold • operates asynchronoulsy at rates up to 100 MHz. • Single photelectron threshold generated by internal DAC. • High speed digital output buffer • X and Y output buffers • Low freq. serial interface to allow uploading of configuration parameters e.g.: • threshold values • mask registers for noisy channels A FINMECCANICA COMPANY

5. ASIC ARCHITECTURE Design Specifications A FINMECCANICA COMPANY

6. OBJECTIVES OF THE STUDY • Technology survey in order to identify suitable technologies on which implement the discriminator cell and whole asic. • Technology survey should identify at least two possible technologies. • Identification of different architectures for the discriminator. • Design, simulation and performance evaluation of F.E. channel on the two selected technologies. A FINMECCANICA COMPANY

7. TECHNOLOGY SELECTION CRITERIA • RADIATION HARDNESS (Total Dose, SEU) (1) • LATCH UP FREE (2) • SPEED & POWER CONSUMPTION (3) • ACCESS TO TECHNOLOGY & DESIGN KIT AVAILABILITY (4) A FINMECCANICA COMPANY

8. TECHNOLOGY SURVEYATMEL DMILL 0.8 m BiCMOS • (1) and (2) : OK • (3) : exhaustive simulation in different worst cases performed on digital CMOS standard cells from design kit. • @ 3.3V commutation and data latch up to 110 MHz achieved. • The digital part of the asic optimised for design and layout can be done in std CMOS (power saving w.r.t. ECL). • The bipolar part of the technology can be used to optimise speed and achieve discriminator performances. • (4) Easy access through Europractice A FINMECCANICA COMPANY

9. TECHNOLOGY SURVEYAMS 0.8 m BiCMOS • (1) : radiation data are not certified by AMS and therefore are not stable in time due to possible changes in technology from AMS. • (2) : the technology is not intrinsically latch up free. • An option to have epi substrate there exists • (3) : the speed performances are better than DMILL both for the digital and analogue part of the technology. • Discriminator performances could be better achieved. • (4) Easy access through Europractice A FINMECCANICA COMPANY

10. TECHNOLOGY SURVEYUMC 0.18 m CMOS • (1) & (2) : no data available up to now but a digital chip is under development by IMEC and a RVT is going to be performed • (3) : Verified on D. K. info basis • (4) : From the available data: • Acquired from IMEC the D.K. with the transistors models. • The technology not officially supported by Europractice but, as IMEC, access to UMC internal MPW runs can be granted. • Waiting for the back-end design kit from Europractice A FINMECCANICA COMPANY

11. TECHNOLOGY SURVEYRESULTS SELECTED TECHNOLOGIES ATMEL DMILL 0.8 m BiCMOS UMC 0.18 m CMOS AMS LEFT AS BACK-UP SOLUTION SINCE PERFORMANCES ARE COMPARABLE WITH DMILL A FINMECCANICA COMPANY

12. DISCRIMINATOR DESIGNCHANNEL ARCHITECTURES • TWO MAIN CHANNEL ARCHITECTURES CONSIDERED: • CURRENT MODE COMPARATOR • Combines in a unique circuit the transimpedance pre-amplifier and the comparator thus allowing to minimise the total power consumption. • VOLTAGE MODE COMPARATOR • Uses Transimpedence Amplifier (TIA) to convert input current in voltage A FINMECCANICA COMPANY

13. DISCRIMINATOR DESIGNCURRENT MODE COMPARATOR (DMILL Technology) Simulation Environment Double Pulse Resolution (worst-case conditions) A FINMECCANICA COMPANY

14. DISCRIMINATOR DESIGNCURRENT MODE COMPARATOR (DMILL Technology) • worst-case minimum input signal • worst-case maximum input signal Cross-talk simulation results A FINMECCANICA COMPANY

15. DISCRIMINATOR DESIGNCURRENT MODE COMPARATOR (UMC Technology) • Single Channel Simulations • worst-case maximum input signal • Single Channel Simulations • worst-case minimum input signal A FINMECCANICA COMPANY

16. DISCRIMINATOR DESIGNCURRENT MODE COMPARATOR DMILL Vs. UMC Technology • Simulated performances DMILL • Simulated performances UMC A FINMECCANICA COMPANY

17. DISCRIMINATOR DESIGNVOLTAGE MODE COMPARATOR DMILL Vs. UMC Technology • Simulated performances (without TIA) DMILL • Simulated performances (without TIA) UMC A FINMECCANICA COMPANY

18. DISCRIMINATOR DESIGNTRANSIMPEDENCE AMPLIFIERDesign Consideration : open loop vs. closed loop • OPEN LOOP • Characteristics • fast • intrinsically stable circuit • bandwidth is limited by the capacitance connected to the input node (necessary to know exactly the capacitance of the input node) • Drawbacks • dynamic range and noise performance • output DC level has a quite large variation over the different worst-cases (determined by the power supply and resistance values) • necessary to use a fully matched “dummy” structure to generate the threshold for the discriminator which tracks the variations of the output DC level of the TIA A FINMECCANICA COMPANY

19. DISCRIMINATOR DESIGNTRANSIMPEDENCE AMPLIFIERDesign Consideration : open loop vs. closed loop • CLOSED LOOP CONFIGURATION • Characteristics • bipolar differential stage with active load • use of bipolar transistors allows to maximise the gain achieved with a single stage for a given biasing current with respect to a CMOS solution. • feedback structure allows to reduce the variations of the output DC level which is now only related to the variations of the feedback resistance • bandwidth and the input referred current noise are inversely related to the feedback resistance value. • Drawbacks • cannot be realised as it is in the UMC technology • An equivalent all CMOS realisation cannot reach similar performance at the same current level due to the much lower gain of MOS transistors • same level of performance could be reached with much larger current consumption or by cascading further gain stages (means larger current consumption too). A FINMECCANICA COMPANY

20. DISCRIMINATOR DESIGNTRANSIMPEDENCE AMPLIFIERDesign Consideration OPEN LOOP CONFIGURATION CLOSED LOOP CONFIGURATION A FINMECCANICA COMPANY

21. DISCRIMINATOR DESIGNTRANSIMPEDENCE AMPLIFIERDesign Consideration • CLOSED LOOP CONFIGURATION • Channel Power Consumption : 980 W • CLOSED LOOP CONFIGURATION • More sensitivity to crosstalk A FINMECCANICA COMPANY

22. SUMMARY AND OPEN POINTS • CIRCUIT ARCHITECTURE • Voltage-mode • voltage-mode discriminator with a closed-loop transimpedance pre-amplifier with quite good performance has been designed in DMILL technology, but with a reduced input signal current range with respect to the current-mode version. Larger power consumption is required to achieve the same performances with UMC. • Current-mode • allows to combine in a unique circuit the pre-amplifier and the comparator thus minimising the total current consumption • more robust to crosstalk interferences between adjacent channels since the common threshold is a current • can be implemented with similar performance in both the DMILL and the UMC technologies. A FINMECCANICA COMPANY

23. LOW-POWER FAST DISCRIMINATORSUMMARY AND OPEN POINTS (cont’d) • EXPECTED DEGRADATIONS DUE TO THE PHYSICAL REALISATION • DMILL • we do not expect large degradation in the performance (based on previous experience) • use of an insulating substrate reduces the parasitics with respect to a standard silicon-substrate process (useful in terms of the crosstalks since a very good isolation between the channels can be achieved) • UMC • we cannot quantify the possible performance degradations with the UMC technology because we do not have any previous silicon feedback on that technology • we can however expect larger degradations with respect to the DMILL technology since this is a standard silicon-substrate structure. A FINMECCANICA COMPANY

24. SUMMARY AND OPEN POINTS (cont’d) • POSSIBLE IMPROVEMENTS • ACHIEVED PERFORMANCES ARE QUITE CLOSE TO TECHNOLOGY LIMITS GIVEN THE LIMITED POWER CONSUMPTION REQUIREMENTS • SMALL REFINEMENTS ON COMPARATOR SENSITIVITY & CURRENT CONSUMPTION ARE STILL POSSIBLE A FINMECCANICA COMPANY

25. SUMMARY AND OPEN POINTS (cont’d) • CONSTRAINTS ON THE OTHER CIRCUITRY (ASSESSMENT) • Digital section placed in cascade to the comparator can be realised fully CMOS in both the technologies with the required speed performance • Current-mode solution allows to remove the need for a pre-amplifier, thus allowing to assign a larger amount of current to the comparator • Necessary to use some external limiting circuitry to bound possible large input current signals below the limit of about 800 µA, being sure not to slow down the input signal edges (current-mode & voltage-mode). • Need to minimise the input capacitance seen by the channel • Need to evaluate the input protection network and limiting circuitry A FINMECCANICA COMPANY

26. SUMMARY AND OPEN POINTS (cont’d) • CIRCUIT ARCHITECTURE • Current-mode is preferable • TECHNOLOGY • DMILL technology seems the most suitable process, since it allows to reach all the performances required with all the analysed architectures BUT A FINMECCANICA COMPANY

27. TECHNOLOGY STATUS • ATMEL STATEMENTS (22-02-2001) << DMILL intrinsic quality not enough to fit visual inspection criteria required for space applications (MIL-STD-2010 Cond A or B). • The extreme low level of space business doesn’t push for process changes. • ATMEL will promote DMILL only for HEP Applications. • Access to technology is granted through EUROPRACTICE (4 runs in 2001 - 2 runs in 2002). • Customer can access dedicated runs (higher costs, higher lead times) • ATMEL will not support neither test nor packaging • DMILL phase-out : 2003 >> A FINMECCANICA COMPANY

28. TECHNOLOGY STATUS • SOLUTIONS? • Push ATMEL to delay tech. Phase-out (ESA contribution ?) • AMS 0.8m BiCMOS with epi sub (needs radiation characterisation) • UMC 0.18m CMOS (needs radiation characterisation) • UTSi 0.5 m CMOS SOS • US Rad Hard process from Peregrine semiconductor. • Available on TIMA-CMP circuit. • Usage, export license and long term availabiliy issues to be investigated ). • U.S. Foundries ? (access to technology & export license issues) • Others ? A FINMECCANICA COMPANY

29. DEVICE QUALIFICATION FLOW FOR SPACE ELECTRONICS • ALL THE MAJOR EUROPEAN TECHNOLGIES WITHIN THE MPW CIRCUITS ARE NOT QUALIFIED FOR SPACE APPLICATIONS. • DEVICES / TECHNOLOGIES THAT ARE INTENDED TO BE USED ON BOARD OF SPACECRAFT ELECTRONIC EQUIPMENTS FOR ESA PROGRAMMES: • THAT ARE NOT FORMALLY QUALIFIED • OR HAVE NOT BEEN ALREADY USED IN HI-REL SPACE APPLICATION • OR WHERE A QUALIFICATION BY SIMILARITY IS NOT POSSIBLE ARE SUBJECT TO TECHNOLOGY EVALUATION • REGARDLESS OF THE TECHNOLOGY TYPE THE FOLLOWING ACTIVITIES ARE MANDATORY: • Technology evaluation . • Radiation Evaluation Test (for non rad-hard technologies). • Screening flow for flight devices. A FINMECCANICA COMPANY

30. DEVICE QUALIFICATION FLOW FOR SPACE ELECTRONICS TECHNOLOGY EVALUATION • PURPOSE OF TECHNOLOGY EVALUATION IS TO OVERSTRESS SPECIFIC CHARACTERISTICS OF THE TECHNOLOGY / MANUFACTURING AND ASSEMBLY PROCESSES AS WELL AS COMPONENT CHARACTERISTICS IN VIEW OF THE DETECTION OF POSSIBLE FAILURE MODES AND TO ENSURE THAT: • Device / technology identified are capable of meeting the required electrical performances. • Device/technology identified are capable of meeting the required physical and environmental performances. • The manufacturer of the device / technology identified is capable of meeting the necessary manufacturing controls. • THE RESULTS OBTAINED WILL BE UTILISED TO ASSESS THE TECHNOLOGY SUITABILITY FOR SPACE APPLICATION AND WILL FORM THE BASIS OF ANY PROCUREMENT OF FLIGHT COMPONENTS. A FINMECCANICA COMPANY

31. DEVICE QUALIFICATION FLOW FOR SPACE ELECTRONICS RADIATION EVALUATION • IF NO RADIATION CHARACTERISATION DATA ARE AVAILABLE, A RADIATION EVALUATION PROGRAM SHALL BE PERFORMED. • TOTAL DOSE, LATCH UP AND SEU SENSITIVITY OF THE TECHNOLOGY SHALL BE ASSESSED FOLLOWING ESA / SCC BASIC SPECIFICATION N° 25100 A FINMECCANICA COMPANY

32. DEVICE QUALIFICATION FLOW FOR SPACE ELECTRONICS FLIGHT LOT PRODUCTION • FLIGHT LOT PRODUCTION COMPRISES THE FOLLOWING ACTIVITIES: • WAFERS PROCUREMENT • PACKAGE PROCUREMENT • WAFER PROBING • CUT, PICK ASSEMBLY and INSPECT GOOD DICE ACCORDING TO ESA/SCC SPEC • VERIFY AND GUARANTEE HERMETICITY OF ASSEMBLED DEVICES • ELECTRICAL TESTS (GO-NO-GO and PERFORMANCE ) • SCREENING ACCORDING TO ESA FLOW • LOT ACCEPTANCE TEST • FULL DATA-LOGGING A FINMECCANICA COMPANY

33. DEVICE QUALIFICATION FLOW FOR SPACE ELECTRONICS • ALL THE ACTIVITIES RELATED TO TECHNOLOGY EVALUATION AND DEVICE QUALIFICATION HAS BEEN ALREADY IMPLEMENTED BY LABEN IN THE FRAME OF ICARUS Front End MIXED SIGNAL ASIC DESIGN AND QUALIFICATION FLOW FOR IBIS INSTRUMENT ON BOARD OF ESA INTEGRAL SATELLITE. A FINMECCANICA COMPANY

34. THINGS TO BE DONE • TECHNOLOGY RE-ASSESSMENT • CIRCUIT PERFORMANCE LIMITS EVALUATION • Input capacitance • Input stage (i.e. PMT I/F) • ASIC ARCHITECTURE ASSESSMENT & SIMULATION • N° of channels • Digital part • DAC • OVERALL ASIC SPECIFICATION ASSESSMENT • INTERCONNECTION & PACKAGING NEEDS • TECHNOLOGY EVALUATION PLAN DEFINITION • PRODUCTION & SCREENING PLAN DEFINITION A FINMECCANICA COMPANY