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System Timing

System Timing. Mark B. Josephs South Bank University, London Mark.Josephs@sbu.ac.uk. A. A. Jerraya. Thematic Area Definition. Research topics asynchronous circuit design, arbitration, metastability clocking schemes, synchronization, skew

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System Timing

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  1. System Timing Mark B. Josephs South Bank University, London Mark.Josephs@sbu.ac.uk A. A. Jerraya

  2. Thematic Area Definition • Research topics • asynchronous circuit design, arbitration, metastability • clocking schemes, synchronization, skew • mixed timing circuits, synchronous/asynchronous interfaces • globally-asynchronous locally-synchronous systems • Research communities • IEEE Async international symposia • ACM/IEEE Tau workshops • European ACiD-WG workshops + summer schools • DATE A6 (also B1 B5 B6 B10)

  3. Paradigm Shift • Increasingly heterogeneous organization of SoC timing • dominance of interconnect delay over gate delay (e.g. multiple clock cycles required for signal to cross chip, impractical to distribute clock across entire chip) • rapid growth of design reuse (e.g. blocks from different design houses, blocks conforming to standardized off-chip interfaces) • Need for better management of power consumption, noise and EM radiation caused by digital circuits • high-performance systems (e.g. cooling problem) • mixed-signal systems (e.g. voltage noise generated on power-supply lines or currents induced in substrate affect A/D conversion, radiation mistaken for radio signal) • secure systems (e.g. data-dependent power consumption and timing reveals information stored on smartcard)

  4. Current Status and Barriers to Overcome • Current status • one company (Philips) marketing asynchronous low-power products (designed using concurrent programming language and associated tools) • several (Intel, Sun) using asynchronous techniques within mainly synchronous products • several startups (Theseus, Fulcrum, Self-Timed Solutions) offering asynchronous design flow • powerful asynchronous logic synthesis tools emerging from academia (UPC, Columbia) • industry and academia experimenting with GALS design • Barriers to Overcome • global-clocking is tried and trusted • system-timing methodologies need to be integrated into standard design flows

  5. Tasks • Long term vision • On-chip modules are islands of self-timed functionality (e.g. implemented in asynchronous logic, or locally-clocked with asynchronous wrapper) • Asynchronous structures provide on-chip interconnect (e.g. asynchronous FIFOs and switches) • Communications-centric EDA (e.g. verification, synthesis and test without global-clock strait-jacket) • Tasks for the first 18 months • organize EuroSoC workshop on system timing • participate in other EuroSoC workshops (e.g. on network-on-chip, design methods & IP reuse, formal methods) • consolidate and extend knowledge (about circuit techniques for synchronization and global signaling, heterogeneous timing in standard design flows,formal verification and synthesis of asynchronous logic) • organize EuroSoC summer school on system timing

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