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RCU to FECs CONNECTORS

Readout Control Unit 1/3. Reconfiguration Auxiliary Devices FLASH Memory FLASH FPGA (ProASIC+). BUS TRANSCEIVERS. FINAL RCU (FECs side). FPGA MAIN FUNCTION Power-on Procedure FEE Initialization Dataflow Control FEE Safety Control. RCU to FECs CONNECTORS. FPGA

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RCU to FECs CONNECTORS

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  1. Readout Control Unit 1/3 • Reconfiguration Auxiliary Devices • FLASH Memory • FLASH FPGA (ProASIC+) BUS TRANSCEIVERS FINAL RCU (FECs side) • FPGA MAIN FUNCTION • Power-on Procedure • FEE Initialization • Dataflow Control • FEE Safety Control RCU to FECs CONNECTORS FPGA XILINX Virtex-II Pro • FPGA for final RCU • Real-time readback of configuration data for verification • Partial reconfiguration while running

  2. Readout Control Unit 2/3 SIU CARD FINAL RCU (links side) DCS CARD Power Regulators

  3. Characterization of Sector A09 • Sector A09 equipped with • backplanes • cooling circuit • LV power rods • LV PS + cables (4 x 40m)

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