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APPENDIX C: MASK OPTION REGISTER

APPENDIX C: MASK OPTION REGISTER. Mask Option Register. An EPROM/OTPROM byte that enables or disables the following options: Operation of low-voltage inhibit module (LVI) during stop mode Resets caused by the LVI module Power to the LVI module

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APPENDIX C: MASK OPTION REGISTER

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  1. APPENDIX C:MASK OPTIONREGISTER

  2. Mask Option Register • An EPROM/OTPROM byte that enables or disables the following options: • Operation of low-voltage inhibit module (LVI) during stop mode • Resets caused by the LVI module • Power to the LVI module • Stop mode ecovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) • EPROM/OTPROM security(1) • STOP instruction • Computer operating properly (COP)

  3. READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET Mask Option Register • LVI Enable in Stop Mode (LVISTOP) • If LVIPWR bit is at logic one, LVISTOP enables the LVI modules to operate during stop mode • 1 = LVI not disabled by STOP instruction • 0 = LVI disabled by STOP instruction • LVI Reset (LVIRST) • Enables reset when LVIOUT is set • MPU remains in reset until VDD rises above LVITRIP • Allow LVISETTLE time before enabling 1 = LVI reset enabled 0 = LVI reset disabled • LVI Power Enable (LVIPWR) • Applies power to the LVI analog circuitry • Disabling will stop current drain form the LVI • 1 = Power applied • 0 = Power not applied

  4. READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD MOR WRITE: RESET: UNAFFECTED BY RESET Mask Option Register • Short Stop Recovery (SSREC) • EnablesCPU to exit stop mode with a short or long delay • 1 = Stop Mode recovery after 32 CGMXCLK cycles • 0 = Stop Mode recovery after 4096 CGMXCLK cycles • EPROM/OTPROM Security (SEC) • Enables EPROM/OTPROM security feature • Setting SEC prevents reading EPROM/OTPROM Contents • 1 = EPROM/OTPROM Security enabled • 0 = EPROM/OTPROM Security disabled • STOP Enable (STOP) • Enables the STOP instruction • 1 = STOP instruction enabled • 0 = STOP instruction treated as illegal opcode • COP Disable (COPD) • Disables COP Module • 1 = COP module disabled • 0 = COP mdoule enabled

  5. Mask Option Register Programming Sequence • Sequence for programming Mask Option Register: 1) Apply VDD + VHI to the IRQ1/VPP pin2) Set the ELAT bit in the EPROM control register 3) Write to the mask option register Note: writing to an invalid address prevents the programming voltage from being applied. 4) Set the EPGM bit 5) Wait for a time, tEPGM .6) Clear the ELAT and EPGM bits note: • Setting the ELAT and EPGM bit with one instruction will set ELAT but clear EPGM. • EPGM must be set by a separate instruction in the programming sequemce.

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