1 / 20

Topic 3c Integer Multiply and Divide

Topic 3c Integer Multiply and Divide. Introduction to Computer Systems Engineering (CPEG 323). Unsigned Integer Multiply. Paper and pencil example: Multiplicand 1000 Multiplier * 1001 1000 0000 0000 1000 Product 01001000. 0. 0. 0. 0. A 3. A 2. A 1.

paul2
Download Presentation

Topic 3c Integer Multiply and Divide

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. Topic 3cInteger Multiply and Divide Introduction to Computer Systems Engineering (CPEG 323) cpeg323-05F\Topic3c-323

  2. Unsigned Integer Multiply • Paper and pencil example: Multiplicand1000Multiplier * 1001 1000 0000 00001000 Product 01001000 cpeg323-05F\Topic3c-323

  3. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 Observation • m bits * n bits = m+n bit product • Stage i accumulates A * 2 i if Bi == 1 cpeg323-05F\Topic3c-323

  4. A3 A2 A1 A0 0 0 0 0 A3 A2 A1 A0 0 0 0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 B3 P7 P6 P5 P4 P3 P2 P1 P0 How does it work? • at each stage shift A left ( x 2) • use next bit of B to determine whether to add in shifted multiplicand • accumulate 2n bit partial product at each stage cpeg323-05F\Topic3c-323

  5. Simple Mathematics A*B • If B has n bits, let the product be productn • 2i*A: shift A left for i times. • It is clear that multiply is composed of iterative • Shift and add Then when B has n+1 bits cpeg323-05F\Topic3c-323

  6. Multiply hardware (V1) Shift Left Multiplicand 64 bits Multiplier 64-bit ALU 32 bits Shift Right Write Product Control 64 bits Note: The multiplicand R, Product R and ALU are all 64-bits, while the Multilier R is 32-bits. cpeg323-05F\Topic3c-323

  7. Start Multiplier0=1 Multiplier0 = 0 1. Test Multiplier0 1a. Add multiplicand to product & place the result in Product register 2. Shift the Multiplicand register left 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes Done Multiply Algorithm (V1) cpeg323-05F\Topic3c-323

  8. Observations on Multiply Version 1 • 1/2 bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in right of of multiplicand as shifted=> least significant bits of product never changed once formed • How many cycles it takes to multiply two 32-bit numbers ? cpeg323-05F\Topic3c-323

  9. Instead of shifting multiplicand to left, shift product to right? cpeg323-05F\Topic3c-323

  10. Multiply hardware (V2) Multiplicand 32 bits Multiplier 32-bit ALU 32 bits Shift right Shift Right Product Control Write 64 bits cpeg323-05F\Topic3c-323

  11. 1. Test Multiplier0 1a. Add multiplicand to the left half ofproduct & place the result in the left half of Product register Multiply Algorithm V2 Start Multiplier0=1 Multiplier0=0 2. Shift the Product register right 1 bit. 3. Shift the Multiplier register right 1 bit. 32nd repetition? No: < 32 repetitions Yes: 32 repetitions cpeg323-05F\Topic3c-323 Done

  12. 0 0 0 0 A3 A2 A1 A0 B0 A3 A2 A1 A0 B1 A3 A2 A1 A0 B2 A3 A2 A1 A0 B3 P7 P6 P5 P4 P3 P2 P1 P0 What’s going on? • Multiplicand stay’s still and product moves right cpeg323-05F\Topic3c-323

  13. Observations on Multiply Version 2 • Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register cpeg323-05F\Topic3c-323

  14. Multiply hardware V3 Multiplicand 32 bits 32-bit ALU Shift right Product (Multiplier) Control Write 64 bits cpeg323-05F\Topic3c-323

  15. 1. Test Product0 1a. Add multiplicand to the left half of product & place the result in the left half of Product register Multiply Algorithm V3 Start Product0 = 0 Product0 = 1 2. Shift the Product register right 1 bit. 32nd repetition? Note: the multiplier is initially Placed in the right ½ of the Product Register No: < 32 repetitions Yes: 32 repetitions cpeg323-05F\Topic3c-323 Done

  16. Sign Multiplication • Easiest solution is to • make both positive • remember whether to • complement product when done That is: calculate the sign of the product, convert the operands into positive numbers, leave out the sign bit, run for 31 steps, then fix the result. cpeg323-05F\Topic3c-323

  17. Faster Algorithms or Multiplication • Booth’s Algorithm • multiply signed numbers using same hardware as before and save cycles • can handle multiple bits at a time • Using an array of adders • Observation: whether to add or not add a particular shifted multiplicand – a decision can be made all in parallel .. cpeg323-05F\Topic3c-323

  18. Divide: Paper & Pencil 1001 Quotient Divisor 1000 1001010 Dividend–1000 10 101 1010–1000 10 Remainder Dividend = Quotient * Divisor + Remainder cpeg323-05F\Topic3c-323

  19. Shift Right Divisor 64 bits Quotient Shift Left 64-bit ALU 32 bits Write Remainder Control 64 bits How to do Division ? Note: Dividend is NOT shifting, and Divisor is moving right! How to do division here ? Note: Left ½ of Divisor R is initialized with the divisor, Right ½ of Remainder R is initialized with dividend, Quotient R is initialized with 0. Try to go over the example on P186 ? cpeg323-05F\Topic3c-323

  20. Division process • step 0: Remainder is initialized with the divident • step 1: The divisor is shift to the right at each step • step 2: And we test if remainder – divisor < 0 ? If so => continue to shift divisor to the right, otherwise set a bit in the quotient R, repeat step 1 with the partial remainder cpeg323-05F\Topic3c-323

More Related