Multiply, divide, and coprocessor

Multiply, divide, and coprocessor PowerPoint PPT Presentation


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Summer 1999. ICOM 4206 - Assembler Basics. Multiplication - basic. CommentsThis is just like decimal multiply ? result is twice as long as inputsUnlike addition or subtraction, unsigned and signed multiply operations are differentWhat is shown is the basic machine multiply, but not the most conve

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Multiply, divide, and coprocessor

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1. Summer 1999 ICOM 4206 - Assembler Basics Multiply, divide, and coprocessor Fixed-point multiply and divide instructions and registers Coprocessor instructions and registers

2. Summer 1999 ICOM 4206 - Assembler Basics Multiplication - basic Comments This is just like decimal multiply – result is twice as long as inputs Unlike addition or subtraction, unsigned and signed multiply operations are different What is shown is the basic machine multiply, but not the most convenient The machine instructions are a signed (mult) and an unsigned multiply (multu) that places a double-length result in hi, lo

3. Summer 1999 ICOM 4206 - Assembler Basics Multiplication - usual Comments This is just like decimal multiply – result is twice as long as inputs Since you are trying to pack a double result in a single register, it can overflow The assembler instructions are a signed and an unsigned multiply that places a single-length result in any register This pseudoinstructions, mul, mulu, mulou assemble into mult or multu followed by a move from lo (mflo)

4. Summer 1999 ICOM 4206 - Assembler Basics The multiplication-related instructions Machine multiplies mult rs, rt # result in hi, lo, can’t overflow multu rs, rt # like mult, but unsigned Moves to/from hi and lo (these are machine instructions) mflo rs # move from lo mtlo rs # move to lo mfhi rs # move from hi mthi rs # move to hi Convenient multiply pseudoinstructions mul rd, rs, rt # signed multiply – without overflow mulo rd, rs, rt # signed multiply – traps overflow mulu rd, rs, rt # unsigned multiply – without overflow mulou rd, rs, rt # unsigned multiply – traps overflow

5. Summer 1999 ICOM 4206 - Assembler Basics Division – basic Comments This is just like decimal division – dividend can be twice as large as divisor and quotient Dividend – upper >divisor gives divide overflow In MIPS, there is no upper dividend The machine instructions are a signed (div) and an unsigned divide (divu) that places a single - length quotient in lo and the remainder in hi There is a divide (rem) pseudoinstruction that places the quotient and discards the remainder There is also a remainder (rem) pseudoinstruction that places the remainder and discards the quotient

6. Summer 1999 ICOM 4206 - Assembler Basics The division-related instructions Machine divides div rs, rt # result in hi, lo, can’t overflow divu rs, rt # like div, but unsigned Moves to/from hi and lo (these are machine instructions) mflo rs # move from lo mtlo rs # move to lo mfhi rs # move from hi mthi rs # move to hi Convenient multiply pseudoinstructions (same opcodes, but 3 registers are specified) div rd, rs, rt # signed multiply – without overflow divu rd, rs, rt # signed multiply – traps overflow

7. Summer 1999 ICOM 4206 - Assembler Basics Coprocessor ideas The usual MIPS has two coprocessors c0 is the exception coprocessor – syscall uses it c1 is the floating-point coprocessor, with its own 32x32 register stack Coprocessor c1 has its own register stack and floating-point ALU Can handle single (32-bit) and double (64-bit) floating arguments Its registers (or pairs) can be loaded or stored with a single instruction, directly to memory Floating-point format is different, we will talk about it later Has a single condition flag, set by the c (compare) instruction Floating-point register contents Can be moved to regular registers without conversion Can also have their contents converted to integer

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