RISC machines

RISC machines PowerPoint PPT Presentation


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RISC machines

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1. RISC machines

2. Software studies (statistical analysis)

3. History

4. History

5. RISC vs CISC: characteristics RISC CISC 1. simple instns taking 1. complex instns taking 1 cycle multiple cycles 2. only LOADs, STOREs 2. any instn. may access access memory memory 3. designed around pipeline 3. designed around instn. set 4. instns. executed by h/w 4. instns interpreted by microprogram 5. Fixed format instns 5. variable format instns 6. Few instns and modes 6. Many instns and modes 7. Complexity in the compiler 7. Complexity in the microprogram 8. Multiple register sets 8. Single register set

6. RISC design

7. Design issues

10. Register Usage

12. RISC vs CISC

13. CISC vs RISC

14. RISC compilers

15. Example 1: Pentium 4 (CISC) Recall: instruction formats [5.13] addressing modes [5.26] Instruction set: [5.33] CISC instruction set design determined for back-compatability superscalar microprocessor tries to “deconstruct” CISC instns into pipelineable microinstructions erratic variants for instn type, register usage, addressing modes [reference pages] Example 2: Intel 8051 Simple CISC instn set standard data movement, arithmetic powerful bit manipulation instructions

16. Example 3: UltraSparc III Recall: formats [5.14] addressing: either immediate or register only load, store access memory [5.34]

17. Example 4: MIPS R4000

19. Summary Pentium 4: 2-address, 32-bit CISC irregular back-compatible UltraSPARC 3-address, 64-bit RISC 128-bit bus somewhat complex formats Intel 8051 simple CISC instns good bit manipulation 4 register sets for efficient interrupt processing MIPS another 64-bit RISC

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