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STAR-TOF DOE Review TDC Electronics. @BNL 25 September 2006. Contents. Status summary Development plan Test / Production plan. 1. Status Summary. Well-tested prototypes are being redesigned to optimize the system and to add a final data aggregation layer.
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STAR-TOF DOE ReviewTDC Electronics @BNL 25 September 2006
Contents • Status summary • Development plan • Test / Production plan
1. Status Summary • Well-tested prototypes are being redesigned to optimize the system and to add a final data aggregation layer. • Substantial non-technical delay places TDC board (TDIG) changes on critical path • Run 7 installation and test will include the new production TDIG and TCPU designs, as well as all major system components and interfaces • Test / Production planning and design have begun in parallel
Run 5 TDC system timing performance Start-timing resolution for 200 GeV (blue) and the 62 GeV (magenta) Cu+Cu data from Run-5 TDIG data from RHIC Run 5. Photomultiplier inputs to TDIG. (http://wjllope.rice.edu/~TOF/TOFr5/Run5data/)
Run 5 TDC system functional performance PID cuts for electrons (upper left) through protons (lower right) in 1/beta-space for the 200 GeV data. TDIG data from RHIC Run 5. (http://wjllope.rice.edu/~TOF/TOFr5/Run5data/)
2. Development Plan • TDIG changes • TCPU changes • System integration • Tray-level cosmic testing at UT • Tray-level installation at STAR for Run 7
Major non-changes to TDIG / TCPU • HPTDC operation: • configuration • control • calibration • data readout • HPTDC performance metrics • LVDS data transfer between boards • STAR integration – Trigger and DAQ • Microprocessor and programmable logic firmware
TDIG change summary • Remove discriminators • Front end electronics perform discrimination • Remove 1 of 4 HPTDC chips • Front end electronics perform pulse stretching to allow rising and falling edge timing measurements on the same channel • Add multiplicity data transfer • Attempt to reduce timing measurement crosstalk • Topological randomization (common detector inputs spread across TDCs) • Improved capacitive decoupling of HPTDC power supplies • Improved microprocessor (8 bit to 16 bit – largely code compatible)
All TDIG Changes • Removed 1 HPTDC chip • Rerouted (Reassigned) Event input channels to HPTDC channels • Redesigned Upstream and Downstream signals and connectors • Changed MCU from 8-bit PIC18F to 16-bit PIC24H microcontroller • Changed MCU clock from 20 MHz to 40 MHz • Changed MCU programming from assembly to C-language • Removed external CAN controller (now incorporated within PIC24H) • Added MCU-controlled CAN termination • Removed external RAM from MCU • Moved board-ID (tray-position switch) from FPGA to MCU • Added Silicon Serial Number (unique ID) to MCU I2C bus. • Added power-status monitoring and HPTDC power control • Added USB communication controller • Changed FPGA from Cyclone to Cyclone II • Added CPLD for control of FPGA configuration memories • Removed discriminator circuits (function now on TINO boards) • Removed (-) voltage input. • Added power input from TINO board. • Added test signal output to TINO board. • Added analog temperature input from TINO board • Removed 2 temperature monitors.
Major changes to TCPU • Remove trigger command input and programmable logic for processing those commands (moved to THUB) • Remove DDL fiber output to DAQ (moved to THUB) • Simplify clock distribution circuitry • Add LVDS output to THUB over CAT6 cable • Add multiplicity output to STAR trigger • Simplify data transfer between boards
3. Test / Production Plan • Production schedule • Test requirements definition • Automated Test system design • TDIG test fixture design • TCPU test fixture design • Production infrastructure
TDIG / TCPU Production Readiness • Parts purchasing and inventory system is in-place. • Vendor / Supplier accounts are in-place. • Multiple vendor/supplier sources for most items identified. • Final Assembly and Testing Area available • Test automation software identified. • Test equipment identified and most is on-hand.
TDIG / TCPU Production Risks • Tray level system test is critical to design validation • Cosmic testing at UT • Run 7 installation • HPTDC shipments from CERN • Apparently in good shape • Need to qualify multiple assembly vendors (and possibly board vendors) • Working with parts distributors on volume purchase agreements with scheduled delivery to reduce lead-time risk
Production test summary • Engineering prototypes will be subject to extensive engineering evaluation and performance testing in-system • Majority of board testing will take place at Blue Sky Electronics • Testing will follow a documented board-level acceptance test procedure • Testing will be automated via fixture design and Labview software environment • Boards and test data will be delivered together, with test data traceable to specific boards
Blue Sky Electronics – TDIG and TCPU Test Remarks • Little or no post-test operations on boards • No jumper changes or baseline firmware reconfiguration • Test what gets shipped; Ship what was tested. • Traceability and firmware configuration management • External and Internal serial number labeling for each board. • Automated test procedures generate archived files in addition to board traveler delivered with board. • Test results available for review if subsequent problems occur. • FPGA / MCU / EPROM checksums or version IDs included in test log. • Firmware changes subject to Engineering Change procedure.
TDIG and TCPU Test (continued) • Failure Analysis • Failure symptom and resolution log kept for review and guidance. • Single failure treated as an anomaly. • Multiple observations of same/similar failure becomes cause for concern. • Concern leads to engineering review of: • Design and execution • Production practice / assembly shop performance • Part sources / handling • Part selection • Testing procedures
TDIG and TCPU Test (continued) • Test sequences may be augmented to capture or evoke late failures or problems observed after delivery. • Test procedures, sequences, and test equipment are documented. • Production tests form the basis of regression test of Engineering Changes. • Test procedure itself subject to Engineering Change procedure.
TDIG and TCPU Test (continued) • Engineering Change Procedure • Why – What is the problem or symptom • Who - is initiating it • What - will be changed (board rev, parts list, etc). • Does it impact boards already shipped? • What happens to work-in progress? • When - is it to happen (become effective). • Confirmation – that the change has happened (how to tell that a particular unit has been changed). • Documentation of Reworks and/or Engineering Changes applied to boards is kept as part of board history (traveler and test files). • Procedure and equipment not ISO-type compliant
