Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module)

1. Firmware & software development Digital Pulse Processor DDC-8 (Universal Trigger Module) Wojtek Skulski University of Rochester W.Skulski Phobos Workshop April/2003

2. Outline • What tools are available? • What needs to be programmed? • 1. GUI. • 2. Embedded mprocessor (8051 derivative). • 3. Digital signal processing FPGA. W.Skulski Phobos Workshop April/2003

3. Software and firmware development tools • Entry-level software development. • All development tools are free. • FPGA: XILINX WebPack ISE. • Embedded micro: Keil C compiler, code restricted to 4kB. • PC GUI: Shareware edition of BlackBox Component Builder. • Expert-level software development. • All tools discounted for universities. • FPGA. • VHDL tools: XILINX ISE, full version. • Graphical tools: MatLab and XILINX System Generator. • Embedded micro: Keil C compiler, full version. • PC GUI: Full edition of BlackBox Component Builder. W.Skulski Phobos Workshop April/2003

4. What needs to be programmed in DDC-8 micro processor FPGA Communication with XLM (if using the combo system). W.Skulski Phobos Workshop April/2003

5. Programming the GUI GUI development system: BlackBox Component Builder • Very robust. • No memory leaks. • No dangling pointers. • Custom graphics. • USB interface. • Free for education. W.Skulski Phobos Workshop April/2003

6. Programming the embedded mprocessor Embedded micro development system: Keil 8051 C compiler • Free intro version. • Full version not free (University discount is available). • Cypress USB framework. • Debugger + monitor available. • Has to be done carefully. W.Skulski Phobos Workshop April/2003

7. Using FPGAs for Digital Signal Processing • What is the advantage of the FPGA over a classic processor? • FPGA is highly parallel, hence better performance. • Data processing can be pipelined. • FPGA becomes an application-specific “custom processor”. • More I/O lines than any processor -> wide data paths. • What is the disadvantage? • More tedious and error prone. • Only integer math is supported, no floating point. • We know how to program processors, we are learning FPGAs only now. • Programming FPGAs has to be done very carefully. W.Skulski Phobos Workshop April/2003

8. Programming the FPGA • Several design methods. • 1. Schematic entry “by hand”. Suitable for small designs. • 2. VHDL programming language. Powerful, but tedious. • 3. Automatic “core generator”. Precompiled “cores” are instantiated. • 4. Graphical LabView-like environment running under MatLab. • Design environments. • A. Free intro version WebPack, only schematic entry and VHDL are provided. • B. Expensive full version ISE XST (University discount is available). • Full version = WebPack + Core Generator. • C. LabView-like MatLab and Simulink environment from MathWorks, Inc. • Programming FPGAs has to be done very carefully. W.Skulski Phobos Workshop April/2003

9. Programming the FPGA using schematic FPGA development system: XILINX ISE W.Skulski Phobos Workshop April/2003

10. Programming the FPGA in VHDL FPGA development system: XILINX ISE W.Skulski Phobos Workshop April/2003

11. Programming the FPGA using Core Generator FPGA development system: XILINX ISE W.Skulski Phobos Workshop April/2003

12. FPGA Graphical Design EnvironmentMatlab+Simulink (MathWorks) & System Generator (XILINX) Slide provided by Steve Pauly spauly@ris-corp.com W.Skulski Phobos Workshop April/2003

13. FPGA Graphical Design Methodology • Draw block diagram • Simulate design • Modify diagram • Generate VHDL • Implement into FPGA • Create bit file • Program FPGA Slide provided by Steve Pauly spauly@ris-corp.com W.Skulski Phobos Workshop April/2003

14. Digital pulse processing in the FPGA Baseline-corrected pulse integral available about 400ns after the input pulse, assuming that all three sums are 100ns long. (Why 400? Remember 300ns latency.) Pulse can be integrated on the fly Pedestal can be subtracted on the fly t0+400ns W.Skulski Phobos Workshop April/2003

15. Reminder concerning 300ns latency Signal from a pocket NIM pulser digitized with the DDC-8 at 40 Msamples/s * 10 bits Excellent response to a very fast pulse seen with the “spy channel” tpulse < tsampling. Digitization made possible by the Nyquist filter ffilter = 1/4 fsampling Latency = 300ns. t0+300ns Input pulse W.Skulski Phobos Workshop April/2003

16. Summary • Three major subsystems to be programmed. • Host PC, embedded microprocessor, FPGA. • Robust, industrial-grade programming tools. • Both the PC and the embedded micro tools are traditional. • The integrated compiler, debugger, etc. • The FPGA programming is new to us. • The promising avenue: graphical FPGA programming. • Firmware & software development will take time. W.Skulski Phobos Workshop April/2003