CSE241A VLSI Digital Circuits Winter 2003 Recitation 8: Project Midpoint Presentations. Group 6 Anuj Grover Puneet Sharma. Successfully added two AES core modules into the top level design No syntactic errors found by DC Synthesized the design successfully
For part a, as we use the time constraint at 5 ns, then we need to optimize the area. We have achieved the timing constraint at that point. We also change some of the script to get better result on the optimization.
For part B, we need to lower the timing constraint and we still figure out this part.
We will do the place and route later of this day after we figure out about the place and route script.
≈1/4 System Complete (Behavior Architecture)
1/3 System Designed
1/3 System Tested
1/6 Design Synthesized
1/6 Design Place&Route
0/6 Design PrimeTime Check
**RC, BK Adders / Array Multiplier Architecture Portion In Progress
3/8-10 Complete Flow and Experiment Runs
3/11-12 Clean-up & Project Writing
Project Report16th Order Digital FIR Project by A. Olsson and C.J. Lee
Optimize for area and power
change set_max_area yields poor results
PartB: Power objective
#2(slack?) 578mWProj10: Moonjung Kyung Weihaw Chuang
Steps done :-
Sample synthesis results :-
Data required time 49.18
Data arrival time -4.56
Slack (MET) 44.62
Combinational area: 164039.734375
Noncombinational area: 36141.289062
Total cell area: 200179.421875
Thank You !