Hardware software co design final project
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Hardware/Software Co-Design Final Project. Emulation on Distributed Simulation Co-Verification System 陳少傑 教授 R91921081 黃鼎鈞 R91943004 尤建智 R91921089 林語亭. Agenda. 1. Introduction of verification 2. Simulation / Emulation 3. Principle of co-verification 4. System Architecture

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Hardware/Software Co-Design Final Project

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Hardware software co design final project

Hardware/Software Co-Design Final Project

Emulation on Distributed Simulation

Co-Verification System

陳少傑 教授

R91921081 黃鼎鈞

R91943004 尤建智

R91921089 林語亭


Agenda

Agenda

  • 1. Introduction of verification

  • 2. Simulation / Emulation

  • 3. Principle of co-verification

  • 4. System Architecture

  • 5. Experiment Result

  • 6. Conclusion

  • 7. Reference


Introduction of verification

Introduction of verification

  • Check if a design correctly implements specified behavior (usually done before manufacture)

  • Classes

  • Logic design verification

  • simulation

  • emulation

  • formal verification

  • Physical design verification


Challenge in soc era

Challenge in SOC Era

  • The complexity and gate count sky-rocket base on Moore Law

  • The chip includes multi-modules( IP ), and mixed signal blocks


Design and verification process

Design and Verification Process

Design: writing design specification and start design cycle

Implement:

Implement and refine the design through all

phases

Verify:

Verify the

Correctness of

design


The verification bottleneck

The Verification Bottleneck

Verification problem grows even faster due to the combination of increased gate count and increased vector count


Approaches to design verification

Approaches to Design Verification

Software Simulation─ traditional software-based simulation

Hardware Accelerated Simulation─ use special purpose hardware to accelerate simulation of circuit

Emulation─ Emulation actual circuit behavior

Rapid Prototyping─ Create a prototype of actual hardware

Formal Verification─ formal method


Simulation emulation verification

Simulation / Emulation Verification

  • Software Simulation: With very high flexibility high extension and more cheaper than emulation

    ----Verilog, VHDL, C/C++, mixed language

  • Hardware Emulation: With very high speed for processing time

    -----PFGA, special hardware


Industrial verification issues

Industrial Verification Issues

Intel: Processor project verification:

“Billions of generated vectors”

“Our VHDL regression tests take 27 days to run. ”

Sun: Sparc project verification:

Test suite ~1500 tests > 1 billion random simulation cycles

“A server ranch ~1200 SPARC CPUs”

Bull: Simulation including PwrPC 604

“Our simulations run at between 1-20 CPS.”

“We need 100-1000 cps.”

Cyrix : An x86 related project

“We need 50x Chronologic performance today.”

“170 CPUs running simulations continuously”

Kodak: “hundreds of 3-4 hour RTL functional simulations”

Xerox: “Simulation runtime occupies ~3 weeks of a design cycle”

Ross: 125 Million Vector Regression tests


Software verification mechanism

Software Verification Mechanism

Monitor or

Rule Check

Library

Simulation Engine

Test Patterns

Design Under Test

Specific outputs


System abstract level simulation

System/Abstract level simulation

  • Easily debug and diagnosis

  • Reduce simulation time

    1. Saving data structure transfer time

    2. Native code predominance

  • Much more memory function

HDL

HDL

HDL

Perl

HDL

HDL

Simulation

Engine

C/C++


Emulation system

Emulation System

  • Advantages:+ easiest to implement (involves little change to the simulation environment)+ 10X to 100X faster than traditional simulation

  • Disadvantages:--All module must be synthesized

    --Difficult to handle verification scripts or mathematical formulas

    --Can’t probe any signal we want (only on input/output)


Sw hw co verification

Design

Test Bench

DUT

SW/HW Co-Verification

Synthesizable DUT and transactor

Transaction-level HDL or C/C++ test bench

transactor

High-level protocol for Communication via network or system bus

Software

simulator

Dedicatedhardware


Principle of co verification

Principle of co-verification

  • How to design an hardware / software co-verification system ?

    ----The key issue is PARTITION


Partition constraint on hardware part

Partition constraint on hardware part

  • Maximum gate-count of FPGA or emulator

  • Maximum number of input and output ports

  • Maximum number of registers in FPGA or emulator

  • Gate-count balance among emulators

  • Delay for critical path in emulator

  • Monitored signal is suitable in hardware


Partition constraint on software part

Partition constraint on software part

  • Communication overhead among simulators and emulators

  • Monitored signal is suitable in hardware

  • Tight clock policy or loose clock policy (multi-clock system)

    ALL of these are test patterns related factors


Partition process flow dynamic process

Partition process flow--Dynamic process

Hardware constraint

Software constraint

Emulator

Partition Engine

HDL file

Simulator

Test Patterns


Incentives of the project

Incentives of the Project

  • Provide earlier verification in IC design process

  • Co-verification among different level description

    • Physical

    • Register Transfer Level

    • Behavior

  • Accelerates verification


Our goal

Our Goal

Simulate 1

Simulate 2

Verilog

VHDL

C

Co-verification

Partition

Manual/Automatic

Emulate 1

Emulate 2


System architecture i

System Architecture (I)

  • Distributed Simulation

Master

TCP/IP port

Child I

Child III

TCP/IP port

TCP/IP port communication

Child II


Features of the simulator

Features of the Simulator

  • A master process

    • must be setup to manipulate communication

  • Several child processes

    • Each corresponds to one part

  • Communication

    • TCP/IP ports


Potential difficulties i

Potential Difficulties (I)

  • Distributed Simulation

    • Synchronization

      • Different simulating speeds among parts

      • The faster have to wait

    • Data communication

      • Communication overhead

        • Partition

      • Clocks are the bottleneck

        • Duplicate global clocks within each parts speedup simulation


System architecture ii

System Architecture (II)

  • Emulation

Master

Simulation

TCP/IP port

TCP/IP port

Child I

Simulation

Child III

Simulation

TCP/IP port

Child II

FPGA

Emulation


Features of the emulator

Features of the Emulator

  • Must be child processes

    • Each corresponds to one part synthesized as EDIF

  • Under the control of a corresponding child simulation

  • Communication

    • Through IDE to its corresponding simulation process


Potential difficulties ii

Potential Difficulties (II)

  • Emulation

    • Synchronization

      • Among FPGA’s and Simulator

        • Clock Signals must be handled by Simulator

      • Among different FPGA’s

        • Simulator synchronize the verification progression

    • Data communication

      • Must be manipulated by the simulator

    • Multiple clocks

      • Handled by Simulator


Potential difficulties iii

Potential Difficulties (III)

  • Design Partition

    • Manual / Automatic

      • Emulation parts must be synthesizable

      • Hardware constrains

    • Communication overhead

      • Among different emulation parts

      • Among different simulation parts


System limitation

System Limitation

  • Emulation

    • Clocks are handled by Simulator, emulation can progress one clock cycle at each call.

    • FPGAs works interruptedly instead at their full speeds.

    • Partition among emulation parts may dominate communication overhead.


Experiment results

Experiment Results

  • RTL module : Jazz2020 (DSP core)

  • Gate Count : 0.5M (estimated)

  • Number of test patterns : 374 (with verification function)

  • Purely software simulation : 183 sec

  • Co-simulation (with Xilinx Vertex 400E) : 94 sec

  • Speed up : 2x (almost) Not fast as we expect


Future work

Future work

  • We will separate RTL code into nonsynthesizable part and synthesizable part

  • Nonsynthesizable Part : Convert to C code (compiled code type) run under embedded CPU on FPGA chip

  • Synthesizable Part : put into FPGA block

  • Goal : All process will be done only on one FPGA chip


Future work1

Future Work

Original

RTL code

non-synthesizable

C Code

Embedded CPU

compiler

Compiled

code

Partition

Engine

FPGA main board

Embedded

CPU

RTL

Gate Level

code

FPGA

Block

FPGA

synthesizer

netlist


Conclusion

Conclusion

  • Simulation is and will be the most popular verification method.

  • Emulation will standout as an accelerator under heavy simulation load.


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