Outline Subreticule B highlights Delayed R.O architecture for the ILC vertex detector CAIRN-3

1. A 12 µm pixel pitch 3D MAPS with delayed and full serial readout for the innermost layer of ILC vertex detector Yunan Fu (on behalf of the CMOS Sensor Group of IPHC) Outline • Subreticule B highlights • Delayed R.O architecture for the ILC vertex detector • CAIRN-3 • Pixel design • Test plan • Summary and perspectives

2. Subreticule B highlights 1 2 3 3’ Digital Tier Analog Tier B Left (BL) B Right (BR) Subcircuit (3) – CAIRN-3 (IPHC, Strasbourg) • 256 x 96 array with a 12 x 24 µm rectangular pixel. • Sensor, Preamp (only NMOS) & Shaper , zero-crossing Discriminator in each analog pixel. • 5-bit TDC & the 2nd hit flag circuitry in each digital pixel. • Serial transmitter (8b/10b encoder & two types of PLLs) • 10-bit low power consumption DAC • Test circuitry for the front-end electronics. Future goal: Separating analog tier into two tiers and reduce the pixel size to 12 x 12 µm. Subreticule B– Three subcircuits: • 1) 2 separate memory cores (CMP) • 2) MAPS for ILC (IRFU, IPHC) • 42x240 array, 20 µm pixel MAPS operating in rolling shutter mode (80 ns/row). • 3) MAPS for ILC(IPHC) • 256 x96 array, 12 x 24 µm rectangular pixel MAPS operating in Delayed readout mode. Future goal: 7-bit TDC & 2nd hit flag in a 12 µm digital pixel IPHC yunanfu@ires.in2p3.fr

3. Delayed R.O. Architecture for the ILC vertex detector • Try 3D architecture based on a 12 µm pixel pitch, motivated by : • <3 µm single point resolution with binary output • Probability to fire a pixel more than once << 10% • Adapted to the ILC beam time (detection phase =1 ms, readout phase~199 ms) • 12 µmpitch pixel with a 2nd hit flag operating in delayed R.O mode • sp >~ 2.5 μm, Probability to fire a pixel more than once ~5% • Explore 3DIT advantages  Split signal collection and processing functionalities • Tier 1 : Process adapted to charge collection, high or normal res EPI (ex. XFAB process) • Tier 2 : Analogue tier: Shaper & discriminator • Tier 3 : Digital tier: 7-bit TDC + 2nd hit flag using an advanced CMOS process (ex.<< 100 nm). • 2 tiers technology  combine charge collection tier and analogue tier together • 12 x 24 µmrectangular pixel for the first prototype step • Tier 1- A : Sensing diode & preamplifier (only NMOS) • Tier 1- B : Shaper & discriminator • Tier 2 : 5-bit TDC & 2nd hit flag (Tint = 31 µs) Propose Future Detector diode + Preamplifier (DP) Shaper + Discriminator (SD) 5-bit time stamping capture + Flag the 2nd Hit circuitry (TS&R.O) DP Future TSV SD TS&R.O Now 12 µm 12 µm IPHC yunanfu@ires.in2p3.fr

4. CAIRN-3 • PLLs (10 MHz 160 MHz) Loop fliter--------------- - 2-order loop fliter - Parameter programable loop fliter • Testablity (FEE): DC feedback------------ - Con.time MOS Res - Time-invariant shaper Digital Pixels • Bias voltage generator - For the sake of power, It adaptes to the ILC beam time. • 5-bit Gray counters Snake-like structure Readout • Clock tree • Pixel array: 128 x 96 In each pixel (24X12 µm) : - Sensor - Front-end electronics • Pixel array: 256 x 96 - 5-bit time stamping capture - the 2nd hit Flag Analog Pixels • Pixel array: 128 x 96 In each pixel (24X12 µm) : - Calibrated test circuit - Front-end electronics • HIT encoder • 7-bit digital signal (200 KHz) • 8b/10b encoder -Full serial readout (100 MHz) • 10-bit DAC - Test auxiliary block IPHC yunanfu@ires.in2p3.fr

5. Vth Analogue Pixel DO<4:2> D Q DO<5> DC feedback DO<1> TI DI<5> Flag Bit S1 DO<0> TE READ_test Vref S2 OUT MUX CLK CLK Scan flip flop READ D Q DO<4:0> G~5 Amp Amp 5 BITS TIME STAMP OUT TI DI<4:0> 5-Bit TDC MOSCAP TE READ_test CS Amp Shaper Discriminator DO<5> MUX CLK Power_on Power_on CLK GND 5 Scan flip flops READ_test Pixel design Digital Pixel Test Work IPHC yunanfu@ires.in2p3.fr

6. Test Plan • Laboratory tests : • Test PLLs / DAC circuitry independently. • Test front-end electronics. • Validation design of the digital pixel in emulating hits and shift readout test mode. • Validation of 8b/10b interface. • Fe55 test in the Laboratory : Double-sided bonding top Devices *A *D D* A* Flip Flip D* 10 µm Circuit board *A *D D* A* Horz *A *A 700 µm bottom D* Bonding TOP Wafer Mirror PADs Bonding A* BOM Wafer top A* 10 µm *D *A *D *A *D *D Circuit board 700 µm Mov Devices bottom *A *D Horz *A *D A----Analog tier D----Digital tier IPHC yunanfu@ires.in2p3.fr

7. Summary and perspectives • The 3D 2-tier CMOS MAPS with delayed and full serial readout architecture has been designed and being fabricated. • Small pitch pixel (12 x24 µm): Sensor, front-end electronics and 5-bit TDC (Tint=31µs). • Full serial read-out speed : ~100 MHz. • Test auxiliary blocks such as PLLs, DAC, FEE, 8b/10b interface. • PCB boards have been designed and fabricated. • Future development : • Small feature pitch pixel for 3D MAPS • Use best suited technology adapted to charge collection (ex.XFAB) • A 12 µm pixel MAPS with 7-bit time stamping, 2nd hit marker (digital process << 100 nm). • 3D CMOS Rolling Shutter Mode MAPS with fast digital readout(R&D in progress). - Low power dispersion , suitable for large size imager. - In order to further improve the single point resolution, time resolution and save power consumption. • Tier-1 : Sensor + preamplifier + amplifier ( G~500 µV/e-) • Tier-2 : 4-bit RS pixel-level ADC with offset cancellation circuitry ( LSB ~ noise level) • Tier-3 : fast pipeline readout with data sparsification circuitry • See talk of W. Dulinski • See talk of Yavuz DEGERLI IPHC yunanfu@ires.in2p3.fr

8. IPHC yunanfu@ires.in2p3.fr

9. 12 µm Sensor & Amp TSV Shaper & Dis. Low power Rolling shutter mode 7-bit TDC & 2nd Hit Marker Bit 12 µm 5-bit TDC & 2nd Hit Marker Bit Data sparisifaction 18 µm 24 µm A vertically integrated 3D CMOS MAPS with fast pipeline digital readout • 3D CMOS MAPS with fast pipeline digital readout(R&D in progress). • Tier 1: Sensor + preamplifier + amplifier (G~500 µV/e-) • Tier 2: 4-bit pixel-level ADC with offset cancellation circuitry (1LSB ~ noise level) • Tier 3: Fast pipeline readout with data sparisification Using advanced technology (<<100 nm) 1. Tint ~ 7.8 µs Chartered 130 nm 2. sp ~ 2.8 µm Solution 1 7-bit TDC & 2nd Hit Marker Bit 12 µm 3. Delayed R.O 12 µm Future goal 12 µm Solution 2 Token 18 µm Sensor & Preamp ( 500 µV/e ) 1. Tint ~ 7.0 µs Token 2. sp ~ 2.0 µm sp ~ 2.0 µm Tint ~ 7.0 µs TSV 3. Rolling shutter 4-bit Pixel-ADC ( 20 µW / Pixel ) 18 µm Increasing the pixel pitch (18 µm) Token 18 µm Pipeline Rolling Shutter IPHC yunanfu@ires.in2p3.fr