An overview of serial ata technology
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An Overview of Serial ATA Technology. Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 [email protected] Objectives. Why SATA was invented The differences between PATA and SATA

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An overview of serial ata technology

An Overview of Serial ATA Technology

Chris Erickson

Graduate Student

Department of Electrical and Computer Engineering

Auburn University, Auburn, AL 36849

[email protected]


Objectives

Objectives

  • Why SATA was invented

  • The differences between PATA and SATA

  • How the hardware is structured to transmit and receive SATA

  • Protocol of SATA transmission


What is pata

What is PATA?

  • All of the below synonyms refer to a modern day PATA drive

    • PATA – Parallel Advanced Technology Attachment

    • UDMA – Ultra Direct Memory Access

    • IDE – Integrated Device Electronics

    • EIDE – Enhanced IDE


More on pata

More on PATA

  • 40 & 80 wire cable option

    • 40 wire limited to UDMA 33 MB/s and below

    • 80 wire allowed for UDMA 66, 100, 133 MB/s

  • Required by ATA spec to be 5v tolerant (3.3v has been the norm for several years)

  • Must support Master/Slave/Cable Select


Sata basics

SATA Basics

  • New Connector

    • Saves space

    • More reliable

    • More air flow

  • Connector has 4 transmission wires

    • Tx differential pair

    • Rx differential pair


Sata basics1

SATA Basics

  • SATA I for 1.5Gbps ~ 150MB/s

  • SATA II for 3.0Gbps ~ 300MB/s

  • Provides support for legacy command set

  • Includes new commands for SATA BIST and power management


Connectivity

Connectivity

  • Serial ATA is point-to-point topology

    • Hosts can support multiple devices but requires multiple links

    • 100% available link bandwidth

    • Failure of one device or link does not affect other links


Link characteristics

Link Characteristics

  • SATA uses full-duplex links

    • Protocol only permits frame transfer in one direction at a time

    • Each link consists of a transmit and a receive pair

  • SATA uses low voltage levels

    • Nominal voltage +/-250mV differential


Power management

Power Management

  • SATA has

    • Phy Ready – Capable of sending and receiving data. Main phase locked loop are on and active

    • Partial – Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 us.

    • Slumber – Physical layer is powered but in a reduced state. Must be able to return to Phy Ready within 10 ms.

  • ATA also defines IDLE, STANDBY, and SLEEP

  • Necessary for newer laptop & mobile devices


Sata architectural model

Host Control Software

Buffer Memory

DMA management

Device Control Software

Buffer Memory

DMA management

Serial digital transport control

Serial digital transport control

Serial digital link control

Serial digital link control

Serial physical interface

Serial physical interface

Host Layers

Device Layers

SATA Architectural Model

Application

Transport

Link

Physical


Physical layer

Physical Layer

  • Transmission (Tx) and Reception (Rx) of a 1.5Gb/s serial stream

  • Perform power on sequencing

  • Perform speed negotiation

  • Provide status to link layer

  • Support power management requests

  • Out-of-Band (OOB) signal generation and detection


Out of band

Out of Band

  • Part of normal power on sequence

  • Allows host to issue a device hard reset

  • Allows device to request a hard reset

  • Brings device out of low power state


Out of band signals

Out of Band Signals

  • COMRESET

    • Always originated by the host

    • Forces a hard reset in the device

    • Used to start link initialization

  • COMINIT

    • Always originated by the device

    • Requests a link reset

    • Issued by device in response to COMRESET


Out of band signals cont

Out of Band Signals (cont.)

  • COMWAKE

    • Can be originated by either host or device

    • Used as final phase of OOB initialization

    • Used to bring out of low power & test states

      • Exit Partial

      • Exit Slumber

      • Exit BIST


Out of band signal forms

Out of Band Signal Forms

COMRESET / COMINIT

320 ns

106.7 ns

COMWAKE

106.7 ns

106.7 ns


Out of band signaling protocol

Out of Band Signaling Protocol

COMRESET

COMINIT

Host

Device

COMWAKE

COMWAKE


Sata port model

SATA Port Model

Tx +

Serializer

Data In

Tx -

Align Generator

Tx Clock

Phy Reset

Port Control

Logic

Phy Ready

Analog Front End

Slumber

Partial

SPD Select

SPD Mode

System Clock

Deserializer

Rx +

Data Out

Clock & Data Recovery

Rx -

OOB Detect

RX Clock

COMRESET / COMINIT

COMWAKE


Sata architectural model1

Host Control Software

Buffer Memory

DMA management

Device Control Software

Buffer Memory

DMA management

Serial digital transport control

Serial digital transport control

Serial digital link control

Serial digital link control

Serial physical interface

Serial physical interface

Host Layers

Device Layers

SATA Architectural Model

Application

Transport

Link

Physical


Link layer

Link Layer

  • 8b / 10b encoding

  • Scrambles and descrambles data and control words

  • Converts data from transport layer into frames

  • Conduct CRC generation and checking

  • Provides frame flow control


Encoding concepts

Encoding Concepts

  • All 32 bit Dwords are encoded for SATA

    • 32 bits data = 40 bits of transmission

  • Provides sufficient transition density

    • Guarantees transition (0s and 1s) even if data is 0x00 or 0xFF

  • Provides an easy way to detect transmission error


Current running disparity crd

Current Running Disparity (CRD)

  • As each character is encoded a count is maintained of the number of 0’s and 1’s being transmitted

    • More 1’s than 0’s give positive disparity

    • More 0’s than 1’s gives negative disparity

    • Same number gives neutral disparity

  • Only valid values of CRD are -1 and 1

    • Any other value indicates that a transmission error has occurred


Crd crd encoded characters

CRD+ & CRD- Encoded Characters

8b Character 0x3F

0 0 1 1 1 1 1 1

This 10b Character transmitted when CRD negative

This 10b Character transmitted when CRD positive

1 0 1 0 1 1 1 0 0 1

0 1 0 1 0 0 1 0 0 1

This character

6 ones

4 zeros

Disparity +2

This character

4 ones

6 zeros

Disparity -2


Sata primitives

SATA Primitives

  • Convey real-time state information

  • Control transfer of information between host and device

  • Provide host/device coordination


Sata primitives1

SATA Primitives

  • ALIGN – Speed negotiation and at least every 256 Dword

  • SYNC – Used when in idle to maintain bit synchronization

  • CONT – Used to suppress repeated primitives


Sata primitives2

SATA Primitives

  • X_RDY

  • R_RDY

  • R_IP

  • R_OK

  • R_ERR

  • SOF

  • EOF

  • HOLD

  • HOLDA


Sata frame structure

SATA Frame Structure

  • All SATA frames consist of:

    • A start of frame (SOF) delimiter

    • A payload – transport layer information

    • A Cyclic Redundancy Check (CRC)

    • An end of frame (EOF) delimiter

SOF

Payload Data

CRC

EOF


Link layer protocol 1

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

Link Layer Protocol (1)

Host

Device


Link layer protocol 2

SYNC

SYNC

X_RDY

X_RDY

X_RDY

X_RDY

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

Link Layer Protocol (2)

Host

Device


Link layer protocol 3

X_RDY

X_RDY

X_RDY

X_RDY

X_RDY

X_RDY

SYNC

R_RDY

R_RDY

R_RDY

R_RDY

SYNC

Link Layer Protocol (3)

Host

Device


Link layer protocol 4

X_RDY

X_RDY

SOF

DATA

DATA

DATA

R_RDY

R_RDY

R_RDY

R_RDY

R_RDY

R_RDY

Link Layer Protocol (4)

Host

Device


Link layer protocol 5

DATA

DATA

DATA

DATA

DATA

DATA

R_RDY

R_IP

R_IP

R_IP

R_IP

R_RDY

Link Layer Protocol (5)

Host

Device


Link layer protocol 6

DATA

DATA

CRC

EOF

WTRM

WTRM

R_IP

R_IP

R_IP

R_IP

R_IP

R_IP

Link Layer Protocol (6)

Host

Device


Link layer protocol 7

CRC

EOF

WTRM

WTRM

WTRM

WTRM

R_IP

R_IP

R_IP

R_IP

R_IP

R_IP

Link Layer Protocol (7)

Host

Device


Link layer protocol 8

WTRM

WTRM

WTRM

WTRM

WTRM

WTRM

R_IP

R_OK

R_OK

R_OK

R_OK

R_IP

Link Layer Protocol (8)

Host

Device


Link layer protocol 9

WTRM

WTRM

SYNC

SYNC

SYNC

SYNC

R_OK

R_OK

R_OK

R_OK

R_OK

R_OK

Link Layer Protocol (9)

Host

Device


Link layer protocol last

SYNC

SYNC

SYNC

SYNC

SYNC

SYNC

R_OK

SYNC

SYNC

SYNC

SYNC

R_OK

Link Layer Protocol (last)

Host

Device


Sata architectural model2

Host Control Software

Buffer Memory

DMA management

Device Control Software

Buffer Memory

DMA management

Serial digital transport control

Serial digital transport control

Serial digital link control

Serial digital link control

Serial physical interface

Serial physical interface

Host Layers

Device Layers

SATA Architectural Model

Application

Transport

Link

Physical


Transport layer

Transport Layer

  • Responsible for the management of Frame Information Structures (FIS)

  • At the command of Application layer:

    • Format the FIS

    • Make frame transmission request to Link layer

    • Pass FIS contents to Link layer

    • Receive transmission status from Link layer and reports to Application layer


Frame information structure fis

Frame Information Structure (FIS)

  • A FIS is a mechanism to transfer information between host and device application layers

    • Shadow Register Block contents

    • ATA commands

    • Data movement setup information

    • Read and write data

    • Self test activation

    • Unique FIS Type Code


Fis types

FIS types


Register host to device fis

Register – Host to Device FIS


Bist activate fis

BIST Activate FIS

T - Far end transmit only – transmit Dwords defined in words 1 & 2

A - No ALIGN transmission (valid only with T)

S - Bypass scrambling (valid only with T)

L - Far end retimed loopback with ALIGN insertion

F - Far end analog loopback

P - Transmit primitives defined in words 1 & 2 of the FIS

R - Reserved

V - Vendor Unique Test Mode – other bits undefined


Data fis

Data FIS


Sata architectural model3

Host Control Software

Buffer Memory

DMA management

Device Control Software

Buffer Memory

DMA management

Serial digital transport control

Serial digital transport control

Serial digital link control

Serial digital link control

Serial physical interface

Serial physical interface

Host Layers

Device Layers

SATA Architectural Model

Application

Transport

Link

Physical


Command application layer

Command / Application Layer

  • Defined using a series of state diagrams

    • Register H  D

    • Register D  H

    • DMA data in

    • DMA data out

  • Host command layer may be the same but may only support legacy commands


Completed

Completed !!

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