Architectures for baseband processing in future wireless base station receivers
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Architectures for Baseband Processing in Future Wireless Base-Station Receivers. Sridhar Rajagopal ECE Department Rice University March 22,2000. This work is supported by Nokia, Texas Instruments, Texas Advanced Technology Program and NSF. Third Generation Wireless. First Generation

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Architectures for Baseband Processing in Future Wireless Base-Station Receivers

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Architectures for baseband processing in future wireless base station receivers

Architectures for Baseband Processing in Future Wireless Base-Station Receivers

Sridhar Rajagopal

ECE Department

Rice University

March 22,2000

This work is supported by Nokia, Texas Instruments, Texas Advanced Technology Program and NSF


Third generation wireless

Third Generation Wireless

First Generation

Voice

Eg: AMPS

Second/Current Generation

Voice + Low-rate Data (9.6Kbps)

Eg : IS-95(N-CDMA)

Third Generation +

Voice + High-rate Data (2 Mbps) + Multimedia

W-CDMA

CAIN Project


Main parts of base station receiver

Noise +MAI

Base Station

Reflected Paths

Direct Path

User 1

User 2

Main Parts of Base-Station Receiver

  • Channel Estimation

    • Noise, MAI

    • Attenuation

    • Fading

  • Detection

    • Detect user’s information

    • Multiple Users

  • Decoding

    • Coding/Decoding improve error rate Performance

    • Coding done at handset

Wireless Communication Uplink

CAIN Project


Base station receiver

User Interface

Translation

Synchronization

Transport

Network

Physical Layer

OSI

Antenna

Layers

3-7

Multiuser Detector

Data

Decoder

Demux

Data Link Layer

(Converts Frames to Bits)

OSI

Layer

Estimated Amplitudes & Delays

2

Pilot

Channel Estimator

Physical Layer

(hardware;

raw bit stream)

OSI

Layer

1

Base-Station Receiver

CAIN Project


Need for better architectures

5

x 10

Data Rates for a typical DSP Implementation

2

Data Rates

1.5

Data Rate Requirement = 128 Kbps

1

0.5

0

9

10

11

12

13

14

15

Number of Users

Need for Better Architectures

  • Current DSPs need orders of magnitude improvement to meet real-time requirements.

  • Reason

    • Sophisticated Algorithms, Computationally Intensive Operations

    • Floating Point Accuracy

  • Solution

    • Try sub-optimal/iterative schemes

    • Fixed Point Implementation

    • Use structure in the algorithms

      • Parallelism / Pipelining

      • Task Partitioning

    • Bit Level Arithmetic

CAIN Project


Channel estimation an example

Channel Estimation - An example

  • Channel Estimation† includes

    • Matrix Correlations, Matrix Inversions, Multiplications

    • Floating Point Accuracy

    • Need to wait till all bits are received.

  • Modified Channel Estimation Algorithm

    • Matrix Inversion eliminated by Iterative Scheme

      • Based on Gradient / Method of Steepest Descent

    • Negligible effect on Bit error Performance

    • Fixed Point accuracy, Computation spread over incoming bits

    • Features to support Tracking over Fading Channels easily added.

†Maximum Likelihood Based Channel Estimation [C.Sengupta et al. : PIMRC’1998, WCNC’1999]

CAIN Project


Simulations awgn channel

Comparison of Bit Error Rates (BER)

-1

10

-2

BER

10

O(K2N)

MF

ActMF

ML

ActML

O(K2NL)

-3

10

4

5

6

7

8

9

10

11

12

Signal to Noise Ratio (SNR)

Simulations - AWGN Channel

Detection Window = 12

SINR = 0

Paths =3

Preamble L =150

Spreading N = 31

Users K = 15

10000 bits/user

MF – Matched Filter

ML- Maximum Likelihood

ACT – using inversion

CAIN Project


Dsp implementation

DSP Implementation

  • Advantages

    • Programmability

    • Ease of implementation

    • High Performance

    • Low Cost

  • Disadvantages

    • Improvements necessary to meet real-time requirements!

    • Sequential Processing

      • Parallelism not fully exploited

    • Cannot process or store data at granularity of bits.

CAIN Project


Vlsi implementation

VLSI Implementation

  • Task Partition Algorithm into Parallel Tasks

  • Take Advantage of Bit Level Operations

  • Find Area-Time Efficient Architecture

  • Meets Real-Time Requirements!

Task A

Task C

Task B

Time

CAIN Project


Conclusions

Conclusions

  • Better Performance achieved by

    • Modifications in the Algorithm

    • Application Specific Architectures

  • Algorithmic Modifications

    • reduce the complexity of the algorithms

    • develop sub-optimal or iterative schemes.

  • Custom hardware solutions

    • bit level operations and parallel structure.

  • Together, algorithm simplifications and custom VLSI implementation can be used to meet the performance requirements of the Base-Station Receiver.

CAIN Project


Future work

Future Work

  • Analysis for Detection and Decoding

  • Mobile Handsets

    • Mobile handsets have similar algorithms

    • Need to account for POWER too.

  • General Purpose Enhancements [But, VLSI first ]

    • Explore Instruction Set Extensions / Architectures for DSPs

    • Exploit Matrix Oriented Structures

    • Bit Level Support

    • Complex Arithmetic

CAIN Project


Fading channel with tracking

0

10

MF - Static

MF - Tracking

ML - Static

ML - Tracking

-1

10

BER

-2

10

-3

10

4

5

6

7

8

9

10

11

12

SNR

Fading Channel with Tracking

Doppler Frequency = 10 Hz, 1000 Bits,15 users, 3 Paths

CAIN Project


Talk outline

Talk Outline

  • Introduction

  • Need for better Architectures

  • Channel Estimation - An example

  • Simulation Results

  • Implementation Issues

    • General Purpose/Application Specific

  • Conclusions

  • Future Work

CAIN Project


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