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R. Antonicelli ST Belgium, Network Division

Seminar for the Class of Digital Systems Electronics. R. Antonicelli ST Belgium, Network Division. The VHDL simulation environment. Polytechnic of Bari May 5 – 7, 2004. What is simulation good to?.

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R. Antonicelli ST Belgium, Network Division

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  1. Seminar for the Class of Digital Systems Electronics R. Antonicelli ST Belgium, Network Division The VHDL simulation environment Polytechnic of Bari May 5 – 7, 2004

  2. What is simulation good to? • When we write down a VHDL code, we must ensure a good matching between the digital circuit and our model • Thus, we need to check every signal and monitor the source code step by step • With a simulator tool we can easily reach these goals

  3. What simulators are often used? • Modelsim by Mentor Graphics * * * * * • Leapfrog by Cadence * * * • Saber by Cadence * • VSS by Synopsys *

  4. Modelsim EE/SE We discuss now about Modelsim simulator tool

  5. Modelsim EE: Graphic interface Main window

  6. Modelsim EE: Graphic interface Wave window

  7. Modelsim EE: Graphic interface Wave window

  8. Modelsim EE: Graphic interface Structure window

  9. Modelsim EE: Graphic interface Signals window

  10. Modelsim EE: Graphic interface Signals window

  11. Modelsim EE: Graphic interface Variables window

  12. Modelsim EE: Graphic interface List window

  13. Modelsim EE: Graphic interface Source window

  14. Modelsim EE: Lessons Create a new library

  15. Modelsim EE: Lessons Compile a model

  16. Modelsim EE: Lessons Load a design

  17. Modelsim EE: Lessons Running a design

  18. Modelsim EE: Lessons Running a design

  19. Modelsim EE: Lessons Running a design

  20. Modelsim EE: Lessons Managing a design

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