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Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. Arithmetic Circuits. January, 2003. A Generic Digital Processor. Building Blocks for Digital Architectures. Arithmetic unit. Bit-sliced datapath.

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Digital integrated circuits a design perspective

Digital Integrated CircuitsA Design Perspective

Jan M. Rabaey

Anantha Chandrakasan

Borivoje Nikolic

Arithmetic Circuits

January, 2003



Building Blocks for Digital Architectures

Arithmetic unit

Bit-sliced datapath

(adder, multiplier, shifter, comparator, etc.)

-

Memory

- RAM, ROM, Buffers, Shift registers

Control

- Finite state machine (PLA, random logic.)

- Counters

Interconnect

- Switches

- Arbiters

- Bus


An intel microprocessor
An Intel Microprocessor

Itanium has 6 integer execution units like this




Itanium integer datapath
Itanium Integer Datapath

Fetzer, Orton, ISSCC’02





Express sum and carry as a function of p g d
Express Sum and Carry as a function of P, G, D

Define 3 new variable which ONLY depend on A, B

Generate (G) = AB

Propagate (P) = A

B

Å

Delete =

A

B

S

C

D and P

Can also derive expressions for

and

based on

o

Note that we will be sometimes using an alternate definition for

+

Propagate (P) = A

B


The ripple carry adder
The Ripple-Carry Adder

Worst case delay linear with the number of bits

td = O(N)

tadder = (N-1)tcarry + tsum

Goal: Make the fastest possible carry path circuit






Mirror adder
Mirror Adder

Stick Diagram


The mirror adder
The Mirror Adder

  • The NMOS and PMOS chains are completely symmetrical. A maximum of two series transistors can be observed in the carry-generation circuitry.

  • When laying out the cell, the most critical issue is the minimization of the capacitance at node Co. The reduction of the diffusion capacitances is particularly important.

  • The capacitance at node Co is composed of four diffusion capacitances, two internal gate capacitances, and six gate capacitances in the connecting adder cell .

  • The transistors connected to Ci are placed closest to the output.

  • Only the transistors in the carry stage have to be optimized for optimal speed. All transistors in the sum stage can be minimal size.





Manchester carry chain2
Manchester Carry Chain

Stick Diagram


Carry bypass adder
Carry-Bypass Adder

Also called Carry-Skip


Carry bypass adder cont
Carry-Bypass Adder (cont.)

tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum









Look ahead topology
Look-Ahead: Topology

Expanding Lookahead equations:

All the way:



Carry lookahead trees
Carry Lookahead Trees

Can continue building the tree hierarchically.


Tree adders
Tree Adders

16-bit radix-2 Kogge-Stone tree


Tree adders1
Tree Adders

16-bit radix-4 Kogge-Stone Tree


Sparse trees
Sparse Trees

16-bit radix-2 sparse tree with sparseness of 2


Tree adders2
Tree Adders

Brent-Kung Tree


Example domino adder
Example: Domino Adder

Propagate

Generate


Example domino adder1
Example: Domino Adder

Propagate

Generate







The mxn array multiplier critical path
The MxN Array Multiplier— Critical Path

Critical Path 1 & 2










The barrel shifter
The Barrel Shifter

Area Dominated by Wiring


4x4 barrel shifter
4x4 barrel shifter

Widthbarrel ~ 2 pm M



0 7 bit logarithmic shifter
0-7 bit Logarithmic Shifter

A

3

Out3

A

2

Out2

A

1

Out1

A

0

Out0


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