Partitioning

1. Partitioning The Hardware / Software Tradeoff -John Burnette-

2. Systems Requiring Codesign • ASIPs synthesis (Application Specific Instruction-set Processor) • Custom computing machines, for execution acceleration • System on a chip (ASICs with embedded processor) • Embedded systems design

3. Goal of Partitioning Task • Obvious: find implementation that meets specifications at minimal cost • Q: How was it done originally? • A: Developers had to make decisions based on their design experience and expertise. • Q: How can the partitioning task be automated? • A: Lots of crazy math.

4. Varying Environments • It is difficult to develop an all-encompassing partitioning technique • Many different applications • Many different Specifications

5. Varying Environments cont’d Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques”

6. System Model • A system model must be specified. Consider: • Available hardware area • Available software memory size • Hardware execution time • Software execution time • How often is task scheduled • Communication time • Data transfer • synchronization

7. System Model cont’d • How many coprocessors are available? • How is everything connected?

8. Design Quality Attributes • Cost and performance parameters to describe the solution. For example: • What is required hardware area for co-processor? • What is the design latency? • What is the required memory space?

9. A Few Partitioning Methods • Some basic partitioning methods that are considered when developing Codesign partitioning tools. • Simulated Annealing • Kernighan & Lin Heuristic • Hierarchal Clustering • Knowledge-based Partitioning

10. 1st Method Simulated AnnealingKirpatrick, Gelatt, and Vecchi (1983)

11. It’s All About the Cost Function • Main goal: “to measure the quality of a solution and guide the algorithm to the best solution.” [1] • Fixed costs and variable costs should be treated separately • If you already have an FPGA, you might as well use it all at a fixed cost. • Can’t do the same thing with an ASIC

12. Cost Function 1 • Cost function proposed by Lopez and Vallejo: • Fc( ) are corrections terms • Ci is design constraint applied to i-th quality attribute of solution P and is used as a normalization parameter • kciis weight factor for correction terms

13. Cost Function 2 • Some techniques for correcting the cost function: • Mean Square Error Minimization • Barrier Techniques • Penalty Methods

14. Mean Square Error Minimization • Objective is to minimize the mean square error between quality attributes and their corresponding constraints. Recall FPGA example; maximum exploitation results in performance improvement with no added cost. • This should be applied to goals that should be completely fulfilled instead of minimized.

15. Barrier Techniques • Asymptotes are place in the constraint-defined boundaries => cost of any solution outside of the design space is infinity. • Example of a barrier function: • Ensures no hard design constraints are violated.

16. Penalty Methods • Suitable when constraints are not too hard • Do not contribute to cost function when solution is within allowable search space • Solutions around border of exploration region can be accepted if really close

17. Penalty Methods cont’d where The weight factor Kciis most important here.

18. Cooling Schedule • For completeness, it should be mentioned that for simulated annealing to work, a cooling schedule must be provided. • This basically tunes the parameters of the optimization routine for the next execution. It would have to be done manually otherwise

19. Simulated Annealing cont’d • Advantage: generality, can be used to optimize in many environments • Disadvantage: long computation time required

20. 2nd Method Kernighan & Lin Heuristic (1970)

21. K&L Heuristic • Based on iterative improvement • Start with random initial partition • Swap nodes between both sides of partition • Best solution found from swap is used as new initial partition for next iteration • Finishes when no more improvements are achieved

22. K&L Heuristic cont’d • (SLIF) access graph is used to compute design quality parameters • Add values of attributes associated with nodes and edges of system graph

23. K&L Heuristic cont’d • Drawbacks • Design can not be scheduled so time estimation is difficult • Process involves adding node attributes => parallelism of a multiprocessor architecture is ignored.

24. 3rd Method Hierarchical Clustering

25. Hierarchical Clustering • This method groups pairs of partitioning objects based on proximity values between these objects. • Algorithm characterized by: • Closeness function • Cut Level in cluster tree (based on closeness)

26. Hierarchical Clustering cont’d • Algorithm selects the two objects with best time improvement when implemented as hardware; the rest assigned to software process. • Objects are gradually extracted to hardware until all constraints are met.

27. Hierarchical Clustering cont’d • While these primary constraints are met, secondary constraints (ie, memory) can be checked before finishing Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques”

28. Clustering Process Control Scheme Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques”

29. Closeness Function • This function reflects latency of information exchange between different processes. • ∆ti = sti – htirepresents time improvement when object i is moved from software to hardware. • tcomm(vi ,vj ): communication between vi and vj. • qT ,qC , qAare weight factors • Closeness value is greater for objects with bigger difference between hardware and software execution time.

30. Closeness Function cont’d • Really we want to cluster objects that meet our constraints but still use less hardware area, thus the third term. • Term value is greater when the area of the resulting cluster is less than the average system area. • Fourth term helps us group objects with large sized memory; this is important for consideration of memory space. • After closeness is determined and clusters are formed, the hardware, software, and memory space can be determined.

31. 4th Method Knowledge-Based Partitioning proposed by Lopez-Vallejo and Lopez (2003)

32. Knowledge-Based Partitioning • Knowledge acquired by designers can be conserved as partitioning technologies become obsolete. • The knowledge is included in the system. • Knowledge base can be expanded as new cases are considered.

33. Inference Structure

34. Inference Structure cont’d • Four inferences • Match (Heuristic Classification) • Assign • Evaluate • Select

35. Match • Heuristic rules are stored in knowledge base to match input and output variables. • Variables can be: • Hardware • Quite-Hardware • Unkown • Quite-Software • Software • Example: if hw-area is small and time-improvement is high and number-executions are not few then implementation is very hardware

36. Assign • Provides first solution proposal • Allocates part of the processes to hardware and some to software • This step looks at system blocks, their implementation values and the system constraints (like max hardware/software area, memory available) • After the “hardness” of the constraints are considered, a system configuration is composed and initial partition determined.

37. Evaluate • After assignment, computes parameters that will characterize the design. • Based on parameters we get an idea of the quality and acceptability of the design. • Parameters include: • Estimation of required hardware area • Estimation of required memory space • Execution time (latency) • Communication costs (TX and penalty)

38. Select • Purpose: revise proposed solution and search for another proposal. • Two step process: • Diagnosis – how close is the solution to optimum and what corrections are needed? Maybe correct to lower cost, or maybe design doesn’t meet spec yet. • Operation – perform selection of new proposal based on previous info and knowledge base of prior experience.

39. Select Process

40. Knowledge-Based Partitioning cont’d • Advantage: • Can be used over a variety of environments. • Takes advantage of system knowledge and past experience • Disadvantage: • Newer, so not many tools out there that do it this way.

41. Conclusion • Main goal is to find optimized solution • Minimize cost • Minimize Latency • Minimize power use • There is no all-encompassing partitioning tool out there. • Must identify your constraints and environment to choose appropriate partitioning method.

42. Emerging Studies • Lots of attention given to partitioning methods. Verification is open for study. • Currently it is hard to verify an entire HW/SW system • Hard to find incompatibilities across HW/SW boundaries (usually found at prototyping stage) • Codesign tools need to allow us to synthesize controls, events, response times, scheduling • CoWare: http://www.coware.com/portal/page?_pageid=167,105683&_dad=cust_portal&_schema=STAGE • Polis Project: http://www-cad.eecs.berkeley.edu/~polis/ • ImpulseC: http://www.impulsec.com/ • Lots of partitioning studies: http://www-lsi.die.upm.es/publications/publications.html

43. About the Math • For more info on the math for the partitioning methods presented, see • Lopez, J. and Vallejo, M. "On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques.“ ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003 • Also online at: http://www.ee.washington.edu/class/590/peckol/doc/papers/partition1.pdf

44. References • Lopez,J. and Vallejo, M. "On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques. “ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003 • Kirpatrick, S., Gelatt, C., Vecchi, M. “Optimization by Simulated Annealing.” Science 220, 4598, 671-680, 1983 • http://www2.toki.or.id/book/AlgDesignManual/BOOK/BOOK2/NODE92.HTM • http://www.queryplus.com/newsletter_2003q3.htm • http://www.birc.dk/Research/expdata.html • Silva, L., Sampaio, A., Barros, E. "A Constructive Approach to Hardware/Software Partitioning". Formal Methods in System Design, 24, pp. 45-90, 2004 • http://www.ida.ing.tu-bs.de/research/projects/cosyma/overview/node4.html • http://polimage.polito.it/~lavagno/publications/talk/same99.ppt.gz • F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli. “Hardware- Software Co-design of Embedded Systems -- The POLIS approach”. Kluwer Academic Publishers, 1997.

45. References cont’d • M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli. “Hardware/software codesign of embedded systems”. IEEE Micro, 14(4):26--36, August 1994.