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ECE 545 Lecture 5. Data Flow Modeling of Combinational Logic. R equired reading. P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL. Dataflow VHDL Design Style. VHDL Design Styles. dataflow. VHDL Design Styles.

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Data flow modeling of combinational logic

ECE 545

Lecture 5

Data Flow Modeling of Combinational Logic


R equired reading
Required reading

  • P. Chu, RTL Hardware Design using VHDL

    • Chapter 4, Concurrent Signal Assignment

    • Statements of VHDL


Dataflow VHDL Design Style

ECE 448 – FPGA and ASIC Design with VHDL


Vhdl design styles
VHDL Design Styles

dataflow

VHDL Design

Styles

  • Testbenches

behavioral(sequential)

structural

Components and

interconnects

Concurrent

statements

Sequential statements

  • Registers

  • State machines

  • Instruction decoders

Subset most suitable for synthesis


Synthesizable vhdl
Synthesizable VHDL

Dataflow VHDL

Design Style

VHDL code

synthesizable

Dataflow VHDL

Design Style

VHDL code

synthesizable


Register transfer l evel rtl design description
Register Transfer Level (RTL) Design Description

Combinational

Logic

Combinational

Logic

Today’s Topic

Registers


Data-Flow VHDL

Concurrent Statements

  • concurrent signal assignment ()

  • conditional concurrent signal assignment

  • (when-else)

  • selected concurrent signal assignment

  • (with-select-when)

  • generate scheme for equations

  • (for-generate)


Data-flow VHDL

Major instructions

Concurrent statements

  • concurrent signal assignment ()

  • conditional concurrent signal assignment

  • (when-else)

  • selected concurrent signal assignment

  • (with-select-when)

  • generate scheme for equations

  • (for-generate)


Data-flow VHDL: Example

x

y

s

cin

cout


Data-flow VHDL: Example (1)

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY fulladd IS

PORT (x : IN STD_LOGIC ;

y: IN STD_LOGIC ;

cin : IN STD_LOGIC ;

s : OUT STD_LOGIC ;

cout : OUT STD_LOGIC ) ;

END fulladd ;


Data-flow VHDL: Example (2)

ARCHITECTURE dataflow OF fulladd IS

BEGIN

s <= x XOR y XOR cin ;

cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;

END dataflow ;


Logic operators
Logic Operators

  • Logic operators

  • Logic operators precedence

and or nand nor xor not xnor

only in VHDL-93

or later

Highest

not

and or nand nor xor xnor

Lowest


No implied precedence
No Implied Precedence

Wanted: y = ab + cd

Incorrect

y <= a and b or c and d ;

equivalent to

y <= ((a and b) or c) and d ;

equivalent to

y = (ab + c)d

Correct

y <= (a and b) or (c and d) ;


  • E.g.,

    status <= '1';

    even <= (p1 and p2) or (p3 and p4);

    arith_out <= a + b + c - 1;

  • Implementation of last statement

Chapter 4


Signal assignment statement with a closed feedback loop
Signal assignment statement with a closed feedback loop

  • a signal appears in both sides of a concurrent assignment statement

  • E.g., q <= ((not q) and (not en)) or (d and en);

  • Syntactically correct

  • Form a closed feedback loop

  • Should be avoided

Chapter 4


Data-flow VHDL

Major instructions

Concurrent statements

  • concurrent signal assignment ()

  • conditional concurrent signal assignment

  • (when-else)

  • selected concurrent signal assignment

  • (with-select-when)

  • generate scheme for equations

  • (for-generate)


Conditional concurrent signal assignment
Conditional concurrent signal assignment

When - Else

target_signal <= value1whencondition1else

value2whencondition2else

. . .

valueN-1whenconditionN-1else

valueN;


Most often implied structure
Most often implied structure

Value N

Value N-1

Target Signal

Value 2

Value 1

Condition N-1

Condition 2

Condition 1

When - Else

target_signal <= value1whencondition1else

value2whencondition2else

. . .

valueN-1whenconditionN-1else

valueN;

0

1

.…

0

1

0

1


2 to 1 abstract mux
2-to-1 “abstract” mux

  • sel has a data type of boolean

  • If sel is true, the input from “T” port is connected to output.

  • If sel is false, the input from “F” port is connected to output.

Chapter 4





Chapter 4


Chapter 4



Chapter 4


Signed and unsigned types
Signed and Unsigned Types

Behave exactly like

STD_LOGIC_VECTOR

plus, they determine whether a given vector

should be treated as a signed or unsigned number.

Require

USE ieee.numeric_std.all;


Operators
Operators

  • Relational operators

  • Logic and relational operators precedence

= /= < <= > >=

Highest

not

= /= < <= > >=

and or nand nor xor xnor

Lowest


Priority of logic and relational operators
Priority of logic and relational operators

compare a = bc

Incorrect

… when a = b and c else …

equivalent to

… when (a = b) and c else …

Correct

… when a = (b and c) else …



Data-flow VHDL

Major instructions

Concurrent statements

  • concurrent signal assignment ()

  • conditional concurrent signal assignment

  • (when-else)

  • selected concurrent signal assignment

  • (with-select-when)

  • generate scheme for equations

  • (for-generate)


Selected concurrent signal assignment
Selected concurrent signal assignment

With –Select-When

withchoice_expressionselect

target_signal <= expression1whenchoices_1,

expression2whenchoices_2,

. . .

expressionNwhenchoices_N;


Most often implied structure1
Most Often Implied Structure

With –Select-When

withchoice_expressionselect

target_signal <= expression1whenchoices_1,

expression2whenchoices_2,

. . .

expressionNwhenchoices_N;

choices_1

expression1

expression2

choices_2

target_signal

expressionN

choices_N

choice expression


Allowed formats of choices k
Allowed formats of choices_k

WHEN value

WHEN value_1 | value_2 | .... | value N

WHEN OTHERS


Allowed formats of choice k example
Allowed formats of choice_k - example

WITH sel SELECT

y <= a WHEN "000",

c WHEN "001" | "111",

d WHEN OTHERS;


Syntax
Syntax

  • Simplified syntax:

    with select_expression select

    signal_name <=

    value_expr_1 when choice_1,

    value_expr_2 when choice_2,

    value_expr_3 when choice_3,

    . . .

    value_expr_n when choice_n;

Chapter 4


  • select_expression

    • Discrete type or 1-D array

    • With finite possible values

  • choice_i

    • A value of the data type

  • Choices must be

    • mutually exclusive

    • all inclusive

    • others can be used as last choice_i

Chapter 4


E g 4 to 1 mux
E.g., 4-to-1 mux

Chapter 4



E g 2 to 2 2 binary decoder
E.g., 2-to-22 binary decoder

Chapter 4




E g simple alu
E.g., simple ALU

Chapter 4



Conceptual implementation
Conceptual implementation

  • Achieved by a multiplexing circuit

  • Abstract (k+1)-to-1 multiplexer

    • sel is with a data type of (k+1) values:c0, c1, c2, . . . , ck

Chapter 4



Chapter 4 c2, c3, c4


E.g., c2, c3, c4

Chapter 4


3 conditional vs selected signal assignment
3. Conditional vs. selected signal assignment c2, c3, c4

  • Conversion between conditional vs. selected signal assignment

  • Comparison

Chapter 4




Comparison
Comparison c2, c3, c4

  • Selected signal assignment:

    • good match for a circuit described by a functional table

    • E.g., binary decoder, multiplexer

    • Less effective when an input pattern is given a preferential treatment

Chapter 4


  • Conditional signal assignment: c2, c3, c4

    • good match for a circuit a circuit that needs to give preferential treatment for certain conditions or to prioritize the operations

    • E.g., priority encoder

    • Can handle complicated conditions. e.g.,

Chapter 4



MLU Example circuit.


Mlu block diagram
MLU Block Diagram circuit.

MUX_0

0

1

0

1

0

1

A1

A

MUX_4_1

Y1

IN0

MUX_1

NEG_A

IN1

MUX_2

Y

OUTPUT

IN2

SEL0

IN3

SEL1

NEG_Y

B1

B

L1

L0

MUX_3

NEG_B


Mlu entity declaration

LIBRARY ieee; circuit.

USE ieee.std_logic_1164.all;

ENTITY mlu IS

PORT(

NEG_A : IN STD_LOGIC;

NEG_B : IN STD_LOGIC;

NEG_Y : IN STD_LOGIC;

A : IN STD_LOGIC;

B : IN STD_LOGIC;

L1 : IN STD_LOGIC;

L0 : IN STD_LOGIC;

Y : OUT STD_LOGIC

);

END mlu;

MLU: Entity Declaration


Mlu architecture declarative section

ARCHITECTURE mlu_dataflow OF mlu IS circuit.

SIGNAL A1 : STD_LOGIC;

SIGNAL B1 : STD_LOGIC;

SIGNAL Y1 : STD_LOGIC;

SIGNAL MUX_0 : STD_LOGIC;

SIGNAL MUX_1 : STD_LOGIC;

SIGNAL MUX_2 : STD_LOGIC;

SIGNAL MUX_3 : STD_LOGIC;

SIGNAL L:STD_LOGIC_VECTOR(1 DOWNTO 0);

MLU: Architecture Declarative Section


Mlu architecture body

BEGIN circuit.

A1<=NOT A WHEN (NEG_A='1') ELSE

A;

B1<=NOT B WHEN (NEG_B='1') ELSE

B;

Y<=NOT Y1 WHEN (NEG_Y='1') ELSE

Y1;

MUX_0<=A1 AND B1;

MUX_1<=A1 OR B1;

MUX_2<=A1 XOR B1;

MUX_3<=A1 XNOR B1;

L <= L1 & L0;

with (L) select

Y1<=MUX_0 WHEN "00",

MUX_1 WHEN "01",

MUX_2 WHEN "10",

MUX_3 WHEN OTHERS;

END mlu_dataflow;

MLU - Architecture Body


Modeling Common Combinational circuit.

Logic Components

Using Dataflow VHDL

ECE 448 – FPGA and ASIC Design with VHDL


W circuit.ires and Buses

ECE 448 – FPGA and ASIC Design with VHDL


Signals
Signals circuit.

SIGNALa : STD_LOGIC;

SIGNALb : STD_LOGIC_VECTOR(7 DOWNTO 0);

a

1

wire

b

bus

8


Merging wires and buses
Merging wires and buses circuit.

a

4

10

d

b

5

c

SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0);

SIGNALc: STD_LOGIC;

SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);

d <= a & b & c;


Splitting buses
Splitting buses circuit.

a

4

10

d

b

5

c

SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNALb: STD_LOGIC_VECTOR(4 DOWNTO 0);

SIGNALc: STD_LOGIC;

SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);

a <= d(9 downto 6);

b <= d(5 downto 1);

c <= d(0);


Fixed Shifters & Rotators circuit.

ECE 448 – FPGA and ASIC Design with VHDL


Fixed shift in vhdl
Fixed circuit.Shift in VHDL

A(1)

A(0)

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3)

A(2)

A

A>>1

AshiftR

‘0’

A(3)

A(2)

A(1)

AshiftR <=


Fixed rotation in vhdl
Fixed circuit.Rotation in VHDL

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);

A(3)

A(2)

A(1)

A(0)

A

A<<<1

ArotL

A(2)

A(1)

A(0)

A(3)

ArotL <=


Buffers circuit.

ECE 448 – FPGA and ASIC Design with VHDL


Tri-state Buffer circuit.

e

x

f

e

= 0

(a) A tri-state buffer

x

f

e

= 1

f

e

x

x

f

0

0

Z

0

1

Z

(b) Equivalent circuit

1

0

0

1

1

1

(c) Truth table



Tri state buffer example 1
Tri-state Buffer – example (1) circuit.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY tri_state IS

PORT ( ena: IN STD_LOGIC;

input: IN STD_LOGIC;

output: OUT STD_LOGIC

);

END tri_state;


Tri state buffer example 2
Tri-state Buffer – example (2) circuit.

ARCHITECTURE dataflow OF tri_state IS

BEGIN

output <= input WHEN (ena = ‘1’) ELSE ‘Z’;

END dataflow;


Multiplexers circuit.

ECE 448 – FPGA and ASIC Design with VHDL


2 to 1 multiplexer
2-to-1 Multiplexer circuit.

s

w

0

0

f

w

1

1

f

s

w

0

0

w

1

1

(b) Truth table

(a) Graphical symbol


Vhdl code for a 2 to 1 multiplexer
VHDL code for a 2-to-1 Multiplexer circuit.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS

PORT ( w0, w1, s : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;

END mux2to1 ;

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN

f <= w0 WHEN s = '0' ELSE w1 ;

END dataflow ;


Cascade of two m ultiplexer s
Cascade of two circuit.multiplexers

w

0

3

0

w

1

y

w

2

1

1

s2

s1


Vhdl code for a cascade of two multiplexers
VHDL code for a circuit.cascade of two multiplexers

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mux_cascade IS

PORT ( w1, w2, w3: IN STD_LOGIC ;

s1, s2 : IN STD_LOGIC ;

f : OUT STD_LOGIC ) ;

END mux_cascade ;

ARCHITECTURE dataflow OF mux2to1 IS

BEGIN

f <= w1 WHEN s1 = ‘1' ELSE

w2 WHEN s2 = ‘1’ ELSE

w3 ;

END dataflow ;


4-to-1 Multiplexer circuit.

s

0

s

s

s

f

1

1

0

w

w

00

0

0

0

0

w

01

w

1

0

1

f

1

w

10

w

2

1

0

2

w

11

3

w

1

1

3

(a) Graphic symbol

(b) Truth table


VHDL code for a 4-to-1 Multiplexer circuit.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mux4to1 IS

PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;

s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

f : OUT STD_LOGIC ) ;

END mux4to1 ;

ARCHITECTURE dataflow OF mux4to1 IS

BEGIN

WITH s SELECT

f <= w0 WHEN "00",

w1 WHEN "01",

w2 WHEN "10",

w3 WHEN OTHERS ;

END dataflow ;


Decoders circuit.

ECE 448 – FPGA and ASIC Design with VHDL


2 to 4 decoder
2-to-4 Decoder circuit.

w

w

y

y

y

y

En

1

0

3

2

1

0

w

y

1

3

1

0

0

0

0

0

1

w

y

0

2

0

1

0

0

1

0

1

y

1

1

1

0

0

1

0

0

y

En

0

1

1

1

1

0

0

0

x

x

0

0

0

0

0

(a) Truth table

(b) Graphical symbol


Vhdl code for a 2 to 4 decoder
VHDL code for a 2-to-4 Decoder circuit.

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS

PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;

En : IN STD_LOGIC ;

y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END dec2to4 ;

ARCHITECTURE dataflow OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;

BEGIN

Enw <= En & w ;

WITH Enw SELECT

y <= “0001" WHEN "100",

"0010" WHEN "101",

"0100" WHEN "110",

“1000" WHEN "111",

"0000" WHEN OTHERS ;

END dataflow ;


Encoders circuit.

ECE 448 – FPGA and ASIC Design with VHDL


Priority encoder
Priority Encoder circuit.

w

w

w

w

y

y

z

3

2

1

0

1

0

0

0

0

0

d

d

0

0

0

0

1

0

0

1

x

0

0

1

0

1

1

x

x

0

1

1

0

1

x

x

x

1

1

1

1

w

0

y

0

w

1

y

1

w

2

z

w

3


Vhdl code for a priority encoder
VHDL code for a circuit.Priority Encoder

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY priority IS

PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;

z : OUT STD_LOGIC ) ;

END priority ;

ARCHITECTURE dataflow OF priority IS

BEGIN

y <= "11" WHEN w(3) = '1' ELSE

"10" WHEN w(2) = '1' ELSE

"01" WHEN w(1) = '1' ELSE

"00" ;

z <= '0' WHEN w = "0000" ELSE '1' ;

END dataflow ;


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