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Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion

Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion. Pietro Babighian , Luca Benini , Alberto Macii , Enrico Macii ISLPED’04. Outline. Introduction Previous Work Algorithm Experimental Results Conclusion. Low Vt logic module. Virtual ground. sleep.

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Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion

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  1. Post-Layout Leakage Power MinimizationBased on Distributed Sleep Transistor Insertion Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii ISLPED’04

  2. Outline • Introduction • Previous Work • Algorithm • Experimental Results • Conclusion

  3. Low Vt logic module Virtual ground sleep high Vt Introduction • Bellow .13 process leakage dominates power consumption • Leakage power = exp(-q*Vt / K*T) • Leakage reduction methods • Dual Vt partition • MTCMOS • State assignment

  4. Outline • Introduction • Previous Work • Algorithm • Experimental Results • Conclusion

  5. Vdd Low Vt logic module Virtual ground Previous Works • MTCMOS • Take a non-negligible amount of time to wake up and re-activate sleep transistor. (long re-activation time) Stand by mode Active mode sleep 0 VDD-Vth Discharge Re-activation time OFF ON

  6. Previous Works • Distributed sleep transistor • Multiple sleep transistors are initiated. • A faster re-activation time Most techniques presented at thelogicandcircuitlevel, and do not takeplacement informationinto account. Cause severe wiring congestion

  7. Outline • Introduction • Previous Work • Algorithm • Experimental Results • Conclusion

  8. Low Vt logic module Virtual ground sleep high Vt Sleep Transistor Insertion in row-based layout local wiring Vdd

  9. Row Compaction & Area Penalty Row Compaction Add sleep transistor Area Penalty

  10. Add cell to cluster Gate 1 Gate 2 Gate n Select a cell No Timing violation? Update maximum current available at sleep transistor Yes sleep Virtual ground Gate Clustering Get Timing & floorplan Information from Layout According to available space Row Compaction available current at sleep transistor Select a sleep transistor A gate by gate exploration of each row No Check all rows? Yes

  11. How to Select Cell? If Arrival time > Re-activation time, zero re-activation delay overhead are paid. Vdd From primary output to primary input Gate 1 Gate 2 Gate n Virtual ground sleep Discharge OFF ON Re-activation time Check whether the cell can be power-gated? 1.Leakage Power? 2.Current? 3.Timing? RT>RT_OH?

  12. Gate 1 Gate 2 Gate N Virtual ground sleep CL Sleep Transistor Sizing

  13. Outline • Introduction • Previous Work • Algorithm • Experimental Results • Conclusion

  14. Experimental Results(1/2) • Delay overhead constraint is set to 5% • Area overhead constraint is set to 5%

  15. Experimental Results(2/2) • Area Penalty

  16. Experimental Results(3/3) • Delay penalty

  17. Outline • Introduction • Previous Work • Algorithm • Experimental Results • Conclusion

  18. Conclusion • Sleep Transistor Insertion : • Driven by a layout-aware cost function • Done with tunable performance and area penalty

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