Jean BERTRAND – CNES QA engineer in charge of VLSI

1. Jean BERTRAND – CNES QA engineer in charge of VLSI Failure of an HN58C1001 based EEPROM

2. Context and Failure Mode By June 2005 during board test in thermal chamber, an EEPROM type MEM8129 from HMP were found unable to program on one bit of one address. • Board test was performed at -25°C, +23°C and +60°C. Voltage is 5.25V. • At -25°C, bit 3 of address 0x17078 is 0 instead of 1. Above -10°C failure does not occur anymore. • Prior to this observation, the part have been programmed 147 time so the number of write accesses is not considered to be the cause of the problem. • This anomaly show the same signature as one device during Lot Acceptance Tests performed by HMP in 1999 (write failure @ -55°C). • As the satellite must be launched by June 2006, project decide to replace the failed part with another from the original lot. Prior usage of this part, all the remaining parts (7 devices) have been tested in full temperature range without failure. • Dismantled device is now in CNES Lab’s for Failure Analysis.

3. Results of Failure Analysis Failure observed on Flight Model can be systematically reproduced. • Temperature threshold of the failure is -10°C. Above this temperature, address 0x17078 works normally. A new element revealed by FA: • The weak bit can be write by extra writing cycles. Between -10°C and -25°C the address is found valid after two write cycle. Between -25°C and -55°C, it require three write cycle. Further investigation are still in discussion: • From the “Product Assurance” point of view, as the defect can be considered generic (trough Nasa Advisory), accurate understanding of root cause of the failure doesn’t matter. Project just have to follow mitigation techniques at system level. • In my opinion, even if cartography of involved structures is achievable with Laser Electro-thermal Stimulation, it probably doesn’t give any valuable indication as the defect is probably due to oxide impurity or other unobservable cause…

4. Remaining Question When failing bit is programmed, what is the long term reliability of the stored data? • On project demand, HTOL can be performed on the part. Is-it a deferent failure mode than those described in NA-GSFC-2005-04 advisory? • Nasa describe some weak bit who loss the stored charge (electron). CNES failure is the impossibility to extract the stored charge (= to inject hole) in the floating gate. So, in my opinion, even if it is the opposite bit error, root cause is related to the same physical phenomenon (oxide impurity ? MNOS Interface trapped charge ? …)