1 / 40

A Novel Synthesis Algorithm for Reversible Circuits

A Novel Synthesis Algorithm for Reversible Circuits. Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani Email: {msaeedi, msedighi, szamani}@ aut.ac.ir Quantum Design Automation Lab, Computer Engineering Department Amirkabir University of Technology Tehran, Iran ICCAD 2007. Outline.

marjoryr
Download Presentation

A Novel Synthesis Algorithm for Reversible Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Novel Synthesis Algorithm for Reversible Circuits Mehdi Saeedi, Mehdi Sedighi*, Morteza Saheb Zamani Email: {msaeedi, msedighi, szamani}@ aut.ac.ir Quantum Design Automation Lab, Computer Engineering Department Amirkabir University of Technology Tehran, Iran ICCAD 2007

  2. Outline • Introduction • Basic Concept • Previous Work • Proposed Synthesis Algorithm • Experimental Results • Future Works • Conclusions

  3. Introduction AND • Boolean reversible functions • n-input, n-output, • Unique output assignment • Example: a 3-input, 3-output function (0,1,2,7,4,5,6,3)

  4. Power dissipation • Landauer’s paper • Every lost bit causes an energy loss • When a computer erases a bit of information, the amount of energy dissipated into the environment is at least kBTln2 • Bennett’s paper • To avoid power dissipation in a circuit, the circuit must be built with reversible gates

  5. Applications of reversible circuits • Low power CMOS design • Reversible 4-bit adder • “A reversible carry-look-ahead adder using control gates”, Integration, the VLSI Journal, vol. 33, pp. 89-104, 2002 • 384 transistors with no power rails • Optical computing • Quantum computing • Each unitary quantum gate is intrinsically reversible

  6. Basic Concept • Definition: A -CNOT is a (k+1)(k+1) gate. It leaves the first k inputs unchanged, and inverts the last if and only if all others are 1. The unchanged lines are referred to as control lines. • Clearly, the -CNOT gates are all reversible. The first three of these have special names. k inputs (k+1)th input

  7. Basic Concept • The zero-CNOT is just an inverter or NOT gate, and is denoted by N. It performs the operation (x)(x1) • The one-CNOT, which performs the operation (y,x)(y,xy) is referred to as a Controlled-NOT , or CNOT (C). • The two-CNOT is normally called a TOFFOLI (T) gate, and performs the operation (z,y,x)(z,y,xyz)

  8. Basic Concept • Reversible gate • Various reversible gates • CNOT-based gates • NOT, CNOT, C2NOT (Toffoli), … • Generalized Toffoli gate • Positive controls • Negative controls

  9. Synthesis of Reversible Circuits High-level Description Synthesis Gate-level circuits Physical Implementation

  10. Synthesis Algorithms Categories • Constructive algorithms • Construct a circuit from a given specification (i.e. truth table, PPRM expansion, decision diagrams, …) • The resulted cost may not be optimized • The time complexity of the algorithm may be too high

  11. Synthesis Algorithms Categories (Cont’d) • Search-based methods • Also called substitution-based methods • Use common sub-expressions to simplify the input function • All possible gates should be evaluated at each step • The best possible gates are selected based on a predefined function • The algorithm convergence is not guaranteed • An extensive exploration is required • A time consuming procedure

  12. Synthesis Algorithms Categories (Cont’d)

  13. Synthesis Algorithms Categories (Cont’d) • Transformation-based algorithms • Used to improve the cost of circuit • Sometimes applied on the results of other algorithms • Usually use templates to optimize a circuit

  14. Synthesis Algorithms Categories (Cont’d) • A transformation based algorithm [18] • Basic algorithm • Uses row-based operations • Output permutation • Tries all n! output permutations to simplify the result • Control input reduction • To reduce the number of control qubits

  15. Synthesis Algorithms Categories (Cont’d) • Bidirectional algorithm • To apply the method in both directions simultaneously • Template matching • A template consists of a sequence of gates to be matched and the sequence of gates to be substituted when a match is found • A time consuming procedure

  16. The Proposed Algorithm • Definition: Output Translation • The application of a reversible CNOT-based gate at the output side of a reversible specification F • The result of using an output translation will also be reversible • Only one function is changed at a time after using an output translation

  17. The Goal of the Algorithm • To generate a set of ordered output translations • When applied to the reversible specification F, generates ai from fi a1 f1 g2 gk g1 a2 f2 an fn

  18. Applying an Output Translation • Lemma 1 explains the results of using an output translation on a given specification: • (a) Applying an output translation, exchanges the location of 2k minterm pairs where k≤n-1

  19. Exchanging Minterm Locations • (b) Exchanging the location of 2k-1 (k=n-m+1) minterm pairs produces the same result as applying an output translation if: • All 2kminterms have the same value on m-1 particular bit locations • The two minterms of each pair differ only in one bit position

  20. Exchanging Minterm Locations • Proof: An output translation CNOTm(f1,f2,…,fm-1,fm) is applied to F where fk for k∈{1 to m-1} can also be a complemented function. • This output translation maps fm to (f1 f2 …fm-1)⊕ fm where the value of (f1 f2 …fm-1)is 1, there are 2k (k=n-m+1) minterms. • By using CNOTm, the location of these 2k minterms are changed. Moreover, it can be checked CNOTm exchanges the locations of all 2k-1 minterm pairs mi : fm = 0and mj : fm = 1.

  21. Exchanging Minterm Locations f1 1 1 1 f2 1 m-1 1 1 f3 1 1 f4 m 0 1 f5 f6 0 0 n-m f7 0 0 Exchange location of minterm pair

  22. Exchanging Minterm Locations • Specification F(a1,a2,…,an) = (f1,f2,…fn) CNOTm(f1,f2,…,fm-1,fm) a1 f1 1 1 1 1 1 1 1 1 a2 f2 1 1 1 1 a3 f3 1 1 1 1 a4 f4 1 0 0 1 a5 f5 0 0 0 a6 0 f6 0 0 0 a7 0 f7 Exchange location of minterm pair

  23. The Proposed Algorithm Find a minterm which differs from it in its jth variable Select the ith minterm of output functions If the new minterm is below the current minterm Mark it as visited If its jth variable is not correct Exchange their locations Mark it as visited

  24. The Proposed Algorithm (Cont’d) If the new minterm is above the current minterm Repeat the previous steps for all minterms and all variables until ak=fk for each k If the new minterm is not in the right location Exchange their locations Mark it as visited

  25. The Proposed Algorithm Input: A reversible specification F (a1, a2, …, an) = (f1 , f2, …, fn) Output: A set of reversible CNOT-based gates which when applied to F produces an identity function. Notation: The ith function (variable) of jth minterm is denoted as fi,mj (ai,mj). Consequently, The ith minterm of jth function (variable) is denoted as mi,fj (mi,aj)

  26. The Proposed Algorithm i = 1; repeat reset all of the 2n minterms to be unvisited. for each minterm mj (j = 1 ... 2n) do if mj is not visited then if fi,mj ≠ai,mj then Extract the set of output translations (gates) based on Lemma 1 i = (i+1) mod n; until fi=ai for each i (1…n)

  27. The Proposed Algorithm begin mark the minterm mj,fi as a visited minterm select the minterm mk,fi which differs from mj,fi in its ith variable if mk,fi is below mj,fi then exchange the locations of mj,fi and mk,fi. (Therefore fi,mj =ai,mj) mark the minterm mk,fi as a visited minterm else if mk,fi is above than mj,fi then if fp,mk ≠ap,mk (p=1...n) for at least one p then exchange the locations of mj,fi and mk,fi. (Therefore fi,mj =ai,mj) mark the minterm mk,fi as a visited minterm end

  28. Example

  29. f1 a1 f2 a2 f3 a3 Gate Extraction Method 1 1 1 1 1 1 1 1 1 1 1 1 f2(new)=f2f1f3 f2(new)=f2f1f3 f3(new)=f3f1f2' Obtained gates should be applied in the reverse order

  30. The Algorithm Convergence • Theorem 1: The proposed algorithm will converge to a possible implementation after several steps • Each output translation does not change the results of the previous ones • Only one function is changed at a time after using an output translation

  31. The Time Complexity • Assumption: At most h gates are needed • Search-based method • n2n-1 gates must be evaluated to select the best possible gates at each step • At most (n2n-1)h gates should be evaluated • The proposed algorithm needs O(h×2n) steps to reach a result

  32. Search-based Tree

  33. Experimental Results

  34. Experimental Results (Cont’d)

  35. Experimental Results (Cont’d)

  36. Experimental Results (Cont’d)

  37. Experimental Results (Cont’d) • All possible 3-input/3-output reversible circuits (8!=40320) are synthesized • Average number of gates per circuit • The proposed algorithm: 7.28 • Average number of steps per circuit = 63.87 • It takes about 4 minutes to synthesize all circuits • 0.006 seconds for each circuit on average

  38. Future Directions • Working on the improvement of the resulting synthesized circuit • By combining the proposed approach and the search-based methods • By selecting the best possible variable at each step

  39. Conclusions • A new non-search based synthesis algorithm was proposed • Several examples taken from the literature are used • The proposed approach guarantees a result for any arbitrarily complex circuit • It is much faster than the search-based ones

  40. Thank you for your attention!

More Related