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ENGG3190 Logic Synthesis “Sequential Circuit Synthesis”

ENGG3190 Logic Synthesis “Sequential Circuit Synthesis”. Winter 2014 S. Areibi School of Engineering University of Guelph. Outline. Modeling synchronous circuits State-based models. Structural models. State-based optimization methods State minimization .

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ENGG3190 Logic Synthesis “Sequential Circuit Synthesis”

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  1. ENGG3190Logic Synthesis“Sequential Circuit Synthesis” Winter 2014 S. Areibi School of Engineering University of Guelph

  2. Outline • Modeling synchronous circuits • State-based models. • Structural models. • State-based optimization methods • Stateminimization. • State minimization for completely specified machines • State minimization for incompletely specified machines. • State encoding • State encoding for two-level logic • State encoding for multiple-level logic • Structural-based optimization methods • Retiming

  3. Combinational vs. Sequential Circuits • Combinational logic are very interesting and useful for designing arithmetic circuits (adders, multipliers) or in other words the Data Path of a computer. • Combinational circuitscannot remember what happened in the past (i.e. outputs are a function of current inputs). • In certain cases we might need to store some info before we proceed with our computation or take action based on a certain state that happened in the past. • Sequential circuits are capable of storing information between operations. • They are useful in designing registers, counters, and CONTROL Circuits, …

  4. Types of Sequential Circuits Two main types and their classification depends on the times at which their inputs are observed and their internal state changes. • Synchronous: State changes synchronized by one or more clocks • Asynchronous: Changes occur independently

  5. What are Sequential Circuits? Some sequential circuits have memory elements. • Synchronous circuits have clocked latches. • Asynchronous circuits may or may not have latches (e.g. C-elements), but these are not clocked. Feedback (cyclic) is a necessary, but not sufficient condition for a circuit to be sequential. Synthesis of sequential circuits is not as well developed as combinational. (only small circuits) Sequential synthesis techniques are not really used in commercial software (except maybe retiming). Sequential verification is a problem.

  6. Synchronous/Asynchronous Time Continuous in value & time Analog Digital Discrete in value & continuous in time Asynchronous Synchronous Discrete in value & time

  7. Comparison • Synchronous • Easier to analyze because can factor out gate delays • Speed of the system is determined by the clock (maybe slowed!) • Asynchronous • Potentially faster • Harder to analyze We will only look at Synchronous Circuits

  8. ---1/1 0 (1010, 0110)/1 ----/1 (--00, 11-0)/0 1 Example in1 in2 out 1 primary inputs primary output in3 in4 Latch Present State The above circuit is sequential since primary output depends on the state and primary inputs. Next State  Registers and Latches (Netlist) State Transition Graph (STG)

  9. Analysis of Sequential Circuits • The behavior of a sequential circuit is determined from: • Inputs, • Outputs, • Present state of the circuit. • The analysis of a sequential circuit consists of: • Obtaining a suitable description that demonstrates the time sequence of inputs, outputs and states (STATE DIAGRAM).

  10. Derive Input Equations Can describe inputs to FF with logic equations

  11. State Table • Similar to truth table with state added • A sequential circuit with `m’ FFs and `n’ inputs needs 2m+n rows in state table.

  12. Input State Diagram Output • An alternative representation to State Table Input/Output “Mealy Model”

  13. State Diagram: Moore Alternative representation for state table Inputs State/Output

  14. Sequential Circuit Types Moore model – outputs depend on states only. Mealy model – outputs depend on inputs & states

  15. Moore vs. Mealy Machine • Moore Machine: • Easy to understand and easy to code. • Might requires more states (thus more hardware). • Mealy Machine: • They are more general than Moore Machines • More complex since outputs are a function of both the state and input. • Requires less states in most cases, therefore less components. • Choice of a model depends on the application and personal preference. • You can transform a Mealy Machine to a Moore Machine and vice versa.

  16. Design Procedure • Design starts from a specification and results in a logic diagram or a list of Boolean functions. • The steps to be followed are: • Derive a state diagram • Reduce the number of states (Optimization) • Assign binary values to the states (encoding) (Optimization) • Obtain the binary coded state table • Choose the type of flip flops to be used • Derive the simplified flip flop input equations and output equations • Draw the logic diagram

  17. 010 100 Present State Next State C B A C+ B+ A+ 0 0 0 x x x 0 0 1 x x x 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 x x x 101 110 011 Synthesis Example • Implement simple count sequence: 000, 010, 011, 101, 110 • Derive the state transition table from the state transition diagram note the don't care conditions that arise from the unused state codes

  18. A+ C+ B+ C C C X 1 0 0 X 0 X 1 X 1 1 0 X 1 X 0 X 0 0 1 X 1 X 1 A A A B B B Don’t cares in FSMs (cont’d) • Synthesize logic for next state functions derive input equations for flip-flops C+ = B B+ = A + B’ C A+ = A’ C’ + AC • Some states are not reachable!! Since they are don’t cares. • Can we fix this problem?

  19. A+ C+ B+ C C C 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 0 1 1 1 1 1 Present State Next State C B A C+ B+ A+ 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 1 1 x A A A B B B Self-starting FSMs • Deriving state transition table from don't care assignment

  20. 010 100 101 110 011 Self-starting FSMs • Start-up states • at power-up, FSM may be in an used or invalid state • design must guarantee that it (eventually) enters a valid state • Self-starting solution • design FSM so that all the invalid states eventually transition to a valid state may limit exploitation of don't cares 001 111 000

  21. Modeling Synchronous Circuits • State-based model • Model circuits as finite-state machines. • Represented by state tables/diagrams. • Lacks a direct relation between state manipulation and corresponding area and delay variations. • You can Applyexact/heuristic algorithms for • State minimization. • State encoding. • Structural-based models • Represent circuit by synchronouslogic network. • You can Apply • Retiming. • Logic transformations(recall Multi Level Synthesis Transformations!!) • State transition diagrams can be: • Transformed into synchronous logic networks by state encoding. • Recovered from synchronous logic networks by state extraction.

  22. General Logic Structure Combinational logic (CL) Sequential elements • Combinational optimization • keep latches/registers at current positions, keep their function • optimize combinational logic in between • Sequential optimization • change latch position/function (retiming)

  23. Overview of FSM Optimization Specification State Minimization Verification/Testing State Encoding Logic/Timing Optimization

  24. State-Based Models: Optimization

  25. Overview of FSM Optimization Initial: FSM description • provided by the designer as a state table • extracted from netlist • derived from HDL description • obtained as a by-product of high-level synthesis • translate to netlist, extract from netlist State minimization: Combine equivalent states to reduce the number of states. For most cases, minimizing the states results in smaller logic, though this is not always true. State assignment: Assign a unique binary code to each state. The logic structure depends on the assignment, thus this should be done optimally. Minimization of a node: in an FSM network Decomposition/factoring: of FSMs, collapsing/elimination Sequential redundancy removal: using ATPG techniques

  26. Formal Finite-State Machine Model • Defined by the quintuple (, , S, , ). • A set of primary inputspatterns . • A set of primary outputs patterns . • A set of states S. • A state transition function •  : SS. • An output function • : S for Mealy models •  : S for Moore models.

  27. State Minimization • Definition: Derive a FSM with similar behavior and minimum number of states. • Aims at reducing the number of machine states • reduces the size of transition table. • State reduction may reduce? • the number of storage elements. • the combinational logic due to reduction in transitions • Types: • Completely specified finite-state machines • No don't care conditions. • Easy to solve. • Incompletely specified finite-state machines • Unspecified transitions and/or outputs. • Intractable problem.

  28. Redundant States: Minimization 0/0 S1 S2 S1 0/0 0/0 0/0 1/1 0/0 1/1 1/1 1/1 1/1 1/0 S3 S4 1/0 S3 S4 0/0 0/0 • Can you distinguish between State S1 and S2? • States S1, S2 seem to be equivalent! • Hence we can reduce the machine accordingly

  29. State Minimization for Completely-Specified FSMs • Def: Equivalent states • Given any input sequence the corresponding output sequences match. • Theorem: Two states are equivalent iff • they lead to identical outputs and • their next-states are equivalent. • Since equivalence is symmetric and transitive • States can be partitioned into equivalence classes. • Such a partition is unique.

  30. Equivalent States • Two states of an FSM are: • equivalent (or indistinguishable) • if for each input they produce the same output and their next states are identical. Si andSjare equivalent and merged into a single state. Si 1/0 Sm Sm 1/0 0/0 Si,j 1/0 0/0 Sj Sn Sn 0/0

  31. Algorithmic State Minimization • Goal– identify and combine states that have equivalent behavior • Reduced machine is smaller, faster, consumes less power. • Algorithm Sketch 1.Place all states in one set 2. Initially partition set based on output behavior 3. Successively partition resulting subsets based on next state transitions 4. Repeat (3) until no further partitioning is required • states left in the same set are equivalent Polynomial time procedure

  32. Equivalent States … Cont • Example: States A . . . I, Inputs I1, I2, Output, Z A and D are equivalent A and E produce same output Q: Can they be equivalent? A: Yes, if B and D were equivalent and C and G were equivalent.

  33. Minimization Algorithm • Stepwise partition refinement. • Let i , i= 1, 2, …., n denote the partitions. • Initially • 1 = States belong to the same block when outputs are the same for any input. • Refine partition blocks: While further splitting is possible • k+1 = States belong to the same block if they were previously in the same block and their next-states are in the same block of k for any input. • At convergence  i+1 =i • Blocks identify equivalent states.

  34. Example … • 1 = {(s1, s2), (s3, s4), (s5)}. • Split s3, s4 • 2 = {(s1, s2), (s3), (s4), (s5)}. • 2 = is a partition into equivalence classes • States (s1, s2) are equivalent.

  35. … Cont .. Example … Original FSM Minimal FSM

  36. … Example Original FSM {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v3' + IN_0' LatchOut_v2' v4.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2' v4.1 = IN_0' LatchOut_v2 LatchOut_v3 + IN_0' LatchOut_v2' v4.2 = IN_0 LatchOut_v1' + IN_0' LatchOut_v1 + IN_0' LatchOut_v2 LatchOut_v3 sis> print_stats pi= 1 po= 1 nodes= 4 latches= 3 lits(sop)= 22 #states(STG)= 5 Minimal FSM {OUT_0} = IN_0 LatchOut_v1' + IN_0 LatchOut_v2 + IN_0' LatchOut_v2' v3.0 = IN_0 LatchOut_v1' + LatchOut_v1' LatchOut_v2‘ v3.1 = IN_0' LatchOut_v1' + IN_0' LatchOut_v2' sis> print_stats pi= 1 po= 1 nodes= 3 latches= 2 lits(sop)= 14 #states(STG)= 4

  37. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 S0 0/0 1/0 S1 S2 0/0 1/0 0/0 1/0 S3 S4 S5 S6 1/0 1/0 1/0 1/0 0/0 0/1 0/0 0/1 State Minimization Example • Sequence Detector for 010 or 110

  38. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1 S2 0 0 0 S1 S3 S4 0 0 1 S2 S5 S6 0 0 00 S3 S0 S0 0 0 01 S4 S0 S0 1 0 10 S5 S0 S0 0 0 11 S6 S0 S0 1 0 Method of Successive Partitions ( S0 S1 S2 S3 S4 S5 S6 ) ( S0 S1 S2 S3 S5 ) ( S4 S6 ) ( S0 S1 S2 ) ( S3 S5 ) ( S4 S6 ) ( S0 ) ( S1 S2 ) ( S3 S5 ) ( S4 S6 ) S1 is equivalent to S2 S3 is equivalent to S5 S4 is equivalent to S6

  39. Input Next State Output Sequence Present State X=0 X=1 X=0 X=1 Reset S0 S1' S1' 0 0 0 + 1 S1' S3' S4' 0 0 X0 S3' S0 S0 0 0 X1 S4' S0 S0 1 0 S0 X/0 S1’ 0/0 1/0 S4’ S3’ X/0 0/1 1/0 Minimized FSM State minimized sequence detector for 010 or 110

  40. Computational Complexity • Polynomially-bound algorithm. • There can be at most |S| partition refinements. • Each refinement requires considering each state • Complexity O(|S|2). • Actual time may depend upon • Data-structures. • Implementation details.

  41. Implication Table Method B C D E F G H I EH AD √ BD CG BD CG √ EH AD AB FG AD CF AD CF CD AC CD AC BC AG AC AF EG AH GHDH GH DH A B C D E F G H

  42. Implication Table Method (Cont.) B C D E F G H I Equivalent states: S1: A, D, G S2: B, C, F S3: E, H S4: I EH AD √ BD CG BD CG √ EH AD AD CF AB FG AD CF BC AG CD AC CD AC AC AF EG AH GHDH GH DH A B C D E F G H

  43. Minimized State Table Original Minimized Number of flip-flops is reduced from 4 to 2.

  44. Incompletely Specified Machines • Next state and output functions have don’t cares. • However, for an implementation,  and  are functions, • thus they are uniquely defined for each input and state combination. • Don’t cares arise when some combinations are of no interest: • they will not occur or • their outputs will not be observed • For these, the next state or output may not be specified. • (In this case,  and  are relations, but of special type. We should make sure we want these as don’t cares.) • Such machines are called incompletely specified.

  45. … State Minimizationfor Incompletely Specified FSMs • Minimum finite-state machine is not unique. • Implication relations make problem intractable. • Example • Replace * by 1. • {(s1, s2), (s3), (s4), (s5)}. Minimized to 4 states

  46. … State Minimizationfor Incompletely Specified FSMs • Minimum finite-state machine is not unique. • Example • Replace * by 0. • {(s1, s5), (s2, s3, s4)}. 0 0 It is now completely specified Unfortunately, there is an exponential number of completely specified FSMs in correspondence to the choice of the don’t care values!!

  47. Example 1/1 1/1 s1 s2 0/0 By adding a dummy state this can be converted to a machine with only the output incompletely specified. Could also specify “error” as the output when transitioning to the dummy state. Alternatively (better for optimization), can interpret undefined next state as allowing any next state. s1 s2 0/0 1/- 0/- 1/- added dummy non-accepting state 1/1 added transitions to all states and output any value d -/- s1 s2 0/0 0/- 0/- 1/-

  48. State Encoding • Binary and Gray encoding use the minimum number of bits for state register • Gray and Johnson code: • Two adjacent codes differ by only one bit • Reduce simultaneous switching • Reduce crosstalk • Reduce glitch

  49. State Encoding • The cost & delay of FSM implementation depends on encoding of symbolic states. • e.g., 4 states can be encoded in 4! = 24 different ways • There are more than n! different encodings for n states. • exploration of all encodings is impossible, therefore heuristics are used • Heuristics Used: • One-hot encoding • minimum-bit change • prioritized adjacency

  50. One-hot Encoding • Uses redundant encoding in which one flip-flop is assigned to each state. • Each state is distinguishable by its own flip-flop having a value of 1 while all others have a value of 0. A 00 S = 0 Z = 1 0 1 S A B C B 01 S = 1 10 C Z = 0 0 1 Z

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