Image “Padding” In Limited-Memory FPGA Systems. MAPLD 2005 Conference Presentation. William Turri ([email protected]) Ken Simone ([email protected]) Systran Federal Corp. 4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431-1672 937-429-9008 x104. Research Requirements.
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Image “Padding” In Limited-Memory
FPGA Systems
MAPLD 2005 Conference Presentation
William Turri ([email protected])
Ken Simone ([email protected])
Systran Federal Corp.
4027 Colonel Glenn Highway, Suite 210
Dayton, OH 45431-1672
937-429-9008 x104
Original Image
Row Transformed Image
0
…
n-1
0
(n/2)
n-1
k
k+(n/2)
Low pass filter
uses 5 taps
High pass filter
uses 3 taps
High-Pass
Low-Pass
d1(k) needs [2k, 2k+2, 2k+1]
k = 0 => [0, 1, 2]
k = 15 => [30, 31, 32]
r1(k) needs [2k-2, 2k-1, 2k, 2k+1, 2k+2]
k = 0 => [-2, -1, 0, 1, 2]
k = 15 => [28, 29, 30, 31, 32]
Index lies beyond the upper
bound of N
Indices lie beyond the lower
and upper bounds of N
…and so must
this value.
Extension minimizes
the degradation
along the image
borders, resulting
from the wavelet
transform being
used.
These values must
be supplied through
some form of
extension…
Odd-Symmetric
…
c
b
a
b
c
x
y
z
y
x
Even-Symmetric
…
b
a
a
b
c
x
y
z
z
y
Periodic
…
x
y
a
b
c
x
y
z
a
b
For the integer 5/3 transform, Odd-Symmetric extension
gives the best numerical results
Values Needed for Odd-Symmetric Extension
c
b
a
b
c
w
x
y
z
y
…and so must
this value.
These values must
be supplied through
some form of
extension…
For k = 0, these values must be generated through extension, giving…
For we get:
This value must be generated through extension, giving…
generalized
For k = 0:
For k = 1 to (N/2 – 2):
These rational forms of the
equations were chosen because
they best suit our hardware design
For k = (N/2 – 1):
Hard-wired right shift by 1
(divide by 2)
d1(k)
d1(k-1)
(registered)
Hard-wired right shift by 2
(divide by 4)
d1(k)
When k = 0, MUX passes d1(k)
to the ADD8, giving
and performing extension.
Otherwise, MUX passes d1(k-1)
to the ADD8, giving
d1(k-1)
r0(2k)
When k = (N/2-1), lower MUX passes
r0(2k) to the ADD8, giving
and performing extension.
Otherwise, lower MUX passes r0(2k+2)
to the ADD8, giving
r0(2k+2)