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Overview of BLACKFIN processor ADSP-BF533 Memory Operations

Overview of BLACKFIN processor ADSP-BF533 Memory Operations. Steve Daeninck, Electrical and Computer Engineering, University of Calgary, Alberta, Canada. To be tackled today. Reference sources Memory configuration and operations Sample instructions Some code examples. Reference Sources.

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Overview of BLACKFIN processor ADSP-BF533 Memory Operations

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  1. Overview of BLACKFIN processorADSP-BF533 Memory Operations Steve Daeninck,Electrical and Computer Engineering, University of Calgary, Alberta, Canada

  2. To be tackled today • Reference sources • Memory configuration and operations • Sample instructions • Some code examples ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  3. Reference Sources • ADSP-BF533 BLACKFIN Processor Hardware Reference, Analog Devices web site. • ADSP-BF533 BLACKFIN Instruction Set Reference, Analog Devices web site. • ENEL619.23 Course, Reference and Laboratory Notes • Check web-pages for links to VisualDSP++, Compiler, Assembler, Linker and other tools • Also see ECE-ADI-Project (link from Dr. Smith Home Page) ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  4. ADSP-BF533 Core Architecture

  5. BF533 Memory Accesses Under the right conditions -- 4 memory accesses at same time 64 bit Instruction Fetch, 2x32 bit Data Loads, 32 bit Data Store PLUS up to 2 ALU(32 bit) and 2 MAC(16 bit) operations at the same time PLUS background DMA activity ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  6. Data Address Generators -- DAG • There is only 1 memory block, but it is broken into 2 sections. • Each DAG goes to L1 Data Memory, DA0 and DA1 are the Data Address Buses. • There are certain memory access conditions that must be met for parallel access. ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  7. Parallel Memory Access 31 30 ………... 3 2 1 0 • Memory is divided into 4Kbyte sub banks. • If both DAGs are addressing the same 4Kbyte bank, and bit 2 of the addresses match, then a collision would occur. 0x0, 0x8, 0x10, 0x18, … would collide 0x4, 0xC, 0x14, 0x1C, … would collide ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  8. DAG register info • Index registers and Pointer registers • I0 – I3 -> (32 and 16 bit addressing) • P0 – P5 -> (32, 16 and 8 bit addressing) • Modify registers M0 – M3, P0 – P5 • Cannot be used in parallel instructions. • Special Hardware for Circular Buffers • Base registers B0 – B3 • Length registers L0 – L3 • Unlike the SHARC, setting the Base register does not set the corresponding Ireg. ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  9. Some memory access instructions Post-Increment Load/Store Preg = [Preg++] Dreg = [Preg++] or W [Preg++] or B [Preg++] with (X|Z) Dreg_half = W [Preg] Dreg = [Ireg] Dreg = [Ireg--] Dreg_half = W [Ireg ++] These instructions can all be reversed for Store instead of Load without any zero (Z) or sign (X) extension. W [Ireg --] = Dreg_half ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  10. Some memory access instructions Indirect Indexed Load/Store Preg/Dreg = [Preg + uimm6m4] or [Preg + uimm17m4] Dreg = W [Preg + uimm5m2] or W [Preg + uimm16m2] with (X|Z) Dreg = B [Preg + uimm15] with (X|Z) Dreg = W [Preg ++ Preg] with (X|Z) Dreg_half = W [Preg ++ Preg] Dreg = [Ireg++Mreg] These instructions can all be reversed for Store instead of Load without any zero (Z) or sign (X) extension. [Preg + uimm6m4] = Preg ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  11. Some Pointer Instructions Preg++ Preg += Preg Preg += imm7 Ireg— Ireg -= Mreg Ireg -= 2 or 4 ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  12. Example code // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  13. Example code .section data1; Indicates placed in data memory .section program; Indicates placed in instruction memory // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  14. Example code .section data1; .GLOBAL _array; .align 4; .var _array[] = {2,3,4,5}; // Alternate style .GLOBAL _array; .align 4; .var _array[4]; // Can also include a “data file” .GLOBAL _array; .var _array[ ] = “file.dat”; // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  15. Example code – poor approach #define sum_R0 R0 #define temp_R1 R1 #define array_pt_P0 P0 P0.L = _array; P0.H = _array; sum_R0 = 0; temp_R1 = [array_pt_P0 + 0]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [array_pt_P0 + 4]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [array_pt_P0 + 8]; etc. // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  16. Better designed code long int sum = 0; long int temp_pt = array; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; USEABLE IN A LOOP // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; sum = sum + array[0]; sum = sum + array[1]; sum = sum + array[2]; sum = sum + array[3]; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  17. Example code – correct, but poor .section program; #define sum_R0 R0 #define temp_R1 R1 #define temp_pt_P0 P0 P0.L = _array; P0.H = _array; sum_R0 = 0; temp_R1 = [temp_pt_P0]; temp_pt_P0 += 4; sum_R0 = sum_R0 + temp_R1; temp_R1 = [temp_pt_P0]; temp_pt_P0 += 4; sum_R0 = sum_R0 + temp_R1; etc. // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; long int temp_pt = array; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  18. Example code -- correct .section program; #define sum_R0 R0 #define temp_R1 R1 #define temp_pt_P0 P0 #define plus4_P1 P1 P0.L = _array; P0.H = _array; plus4_P1 = 4; sum_R0 = 0; temp_R1 = [temp_pt_P0++plus4_P1]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [temp_pt_P0++plus4_P1]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [temp_pt_P0++plus4_P1]; etc. - [Preg++Preg] can’t be used in Parallel - [Ireg++Mreg] can’t be used in Parallel // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; long int temp_pt = array; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  19. Better designed code -- solution #include “cregister_defs.i” .section program; #define sum_R0 R0 #define temp_R1 R1 #define temp_pt_P0 P0 P0.L = _array; P0.H = _array; sum_R0 = 0; temp_R1 = [temp_pt_P0++]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [temp_pt_P0++]; sum_R0 = sum_R0 + temp_R1; temp_R1 = [temp_pt_P0++]; sum_R0 = sum_R0 + temp_R1; Parallel –> R0=R0+R1 (NS) || R1=[P0++]; Parallel –> R0=R0+R1 (NS) || R1=[I0++]; // Global array long int array[4] = {2, 3, 4, 5}; // Program segment long int sum = 0; long int temp_pt = array; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; sum += *temp_pt++; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  20. Example – you tackle Silly Example to demonstrate pointer addressing and Pipeline stalling. static int c_global_var = 0; //this is a global C variable int *global_var_pt = &c_global_var; //global pointer Implement this C code in assembly: *global_var_pt += 12; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

  21. Example – solution #include “cregister_defs.i” .extern _global_var_pt; .section program; #define var_pt_P0 P0 #define c_var_R0 R0 P1.L = _global_var_pt; P1.H = _global_var_pt; var_pt_P0 = [scratch_pt_P1]; NOP; NOP; NOP; c_var_R0 = [var_pt_P0]; c_var_R0 += 12; [var_pt_P0] = c_var_R0; //*global_var_pt += 12; //P1 = &global_var_pt; //var_pt_P0 = global_var_pt; //wait three cycles for P0 to store address //c_var_R0 = *global_var_pt; //c_var_R0 += 12; //*global_var_pt = c_var_R0; ENEL 619.23 -- Review of Blackfin Processor smithmr@ucalgary.ca

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