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Recap: Processor Design is a Process

CS 152: Computer Architecture and Engineering Lecture 9 Designing a Multicycle Processor Randy H. Katz, Instructor Satrajit Chatterjee, Teaching Assistant George Porter, Teaching Assistant. Recap: Processor Design is a Process. Bottom-up

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Recap: Processor Design is a Process

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  1. CS 152: Computer Architectureand EngineeringLecture 9 Designing a Multicycle ProcessorRandy H. Katz, InstructorSatrajit Chatterjee, Teaching AssistantGeorge Porter, Teaching Assistant

  2. Recap: Processor Design is a Process • Bottom-up • Assemble components in target technology to establish critical timing • Top-down • Specify component behavior from high-level requirements • Iterative refinement • Establish partial solution, expand and improve  Instruction Set Architecture processor datapath control Reg. File Mux ALU Reg Mem Decoder Sequencer Cells Gates

  3. Recap: A Single Cycle Datapath Instruction<31:0> nPC_sel Instruction Fetch Unit <11:15> <0:15> <21:25> <16:20> Rd Rt Clk RegDst 1 0 Mux Rt Rs Rd Imm16 Rs Rt RegWr ALUctr 5 5 5 MemtoReg busA Equal MemWr Rw Ra Rb busW 32 32 32-bit Registers 0 ALU 32 busB 32 0 Clk Mux 32 Mux 32 1 WrEn Adr 1 Data In 32 Data Memory Extender imm16 32 16 Clk ALUSrc ExtOp

  4. RegDst func ALUSrc ALUctr ALU Control (Local) op 6 Main Control : 3 6 ALUop 3 op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 R-type ori lw sw beq jump RegDst 1 0 0 x x x ALUSrc 0 1 1 1 0 x MemtoReg 0 0 1 x x x RegWrite 1 1 1 0 0 0 MemWrite 0 0 0 1 0 0 Branch 0 0 0 0 1 0 Jump 0 0 0 0 0 1 ExtOp x 0 1 1 x x ALUop (Symbolic) “R-type” Or Add Add xxx Subtract ALUop <2> 1 0 0 0 x 0 ALUop <1> 0 1 0 0 x 0 ALUop <0> 0 0 0 0 x 1 Recap: The “Truth Table” for the Main Control

  5. . . . . . . op<5> op<5> op<5> op<5> op<5> op<5> . . . . . . <0> <0> <0> <0> <0> op<0> R-type ori lw sw beq jump RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop<2> ALUop<1> ALUop<0> Recap: PLA Implementation of the Main Control

  6. Recap: Systematic Generation of Control OPcode Control Logic / Store (PLA, ROM) • In our single-cycle processor, each instruction is realized by exactly one control command or “microinstruction” • In general, the controller is a finite state machine • Microinstruction can also control sequencing (see later) Decode microinstruction Conditions Instruction Control Points Datapath

  7. The Big Picture: Where are We Now? • The Five Classic Components of a Computer • Today’s Topic: Designing the Datapath for the Multiple Clock Cycle Datapath Processor Input Control Memory Datapath Output

  8. A B 16 16 Cout Cin 16 DOUT Behavioral Models of Datapath Components entity adder16 is generic (ccOut_delay : TIME := 12 ns; adderOut_delay: TIME := 12 ns); port(A, B: in std_logic_vector (15 downto 0); DOUT: out std_logic_vector (15 downto 0); CIN: in std_logic; COUT: out std_logic); end adder16; architecture behavior of adder32 is begin adder16_process: process(A, B, CIN) variable tmp: std_logic_vector (18 downto 0); variable adder_out: std_logic_vector (31 downto 0); variable carry: std_logic; begin tmp := addum (addum (A, B), CIN); adder_out := tmp(15 downto 0); carry :=tmp(16); COUT <= carry after ccOut_delay; DOUT <= adder_out after adderOut_delay; end process; end behavior;

  9. Behavioral Specification of Control Logic entity maincontrol is port(opcode: in std_logic_vector (5 downto 0); ALUop: out std_logic_vector (1 downto 0); equal_cond: in std_logic; extop out std_logic; ALUsrc out std_logic; MEMwr out std_logic; MemtoReg out std_logic; RegWr out std_logic; RegDst out std_logic; nPC out std_logic; end maincontrol; • Decode / Control-store address modeled by Case statement • Each arm of case drives control signals for that operation • just like the microinstruction • either can be symbolic architecture behavior of maincontrol is begin control: process(opcode,equal_cond) constant ORIop: std_logic_vector (5 downto 0) := “001101”; begin -- extop only 0 (no extend) for ORI inst case opcode is when ORIop => extop <= 0; when others => extop <= 1; end case; end process; end behavior;

  10. Abstract View of Our Single Cycle Processor Main Control op • looks like a FSM with PC as state ALU control fun ALUSrc Equal ExtOp MemWr MemWr RegWr MemRd RegDst ALUctr nPC_sel Reg. Wrt ALU Register Fetch Ext Mem Access PC Instruction Fetch Next PC Result Store Data Mem

  11. What’s Wrong with Our CPI=1 Processor? Arithmetic & Logical PC Inst Memory Reg File ALU setup • Long Cycle Time • All instructions take as much time as the slowest • Real memory is not as nice as our idealized memory • Cannot always get the job done in one (short) cycle mux mux Load PC Inst Memory Reg File ALU Data Mem setup mux mux Critical Path Store PC Inst Memory Reg File ALU Data Mem mux Branch PC Inst Memory Reg File cmp mux

  12. Memory Access Time Storage Array • Physics => fast memories are small (large memories are slow) • Question: register file vs. memory • => Use a hierarchy of memories selected word line storage cell address bit line address decoder sense amps mem. bus proc. bus memory L2 Cache Cache Processor 1 time-period 20 - 50 time-periods 2-3 time-periods

  13. storage element Acyclic Combinational Logic storage element Reducing Cycle Time • Cut combinational dependency graph and insert register / latch • Do same work in two fast cycles, rather than one slow one • May be able to short-circuit path and remove some components for some instructions! storage element Acyclic Combinational Logic (A)  storage element Acyclic Combinational Logic (B) storage element

  14. Basic Limits on Cycle Time • Next address logic • PC <= branch ? PC + offset : PC + 4 • Instruction Fetch • InstructionReg <= Mem[PC] • Register Access • A <= R[rs] • ALU operation • R <= A + B Control nPC_sel ALUctr ALUSrc MemWr MemWr RegWr MemRd RegDst ExtOp Reg. File Exec Operand Fetch Instruction Fetch Mem Access PC Next PC Result Store Data Mem

  15. Equal Partitioning the CPI=1 Datapath • Add registers between smallest steps • Place enables on all registers MemWr MemWr RegWr MemRd RegDst nPC_sel ALUSrc ExtOp ALUctr Reg. File Exec Operand Fetch Instruction Fetch Mem Access PC Next PC Result Store Data Mem

  16. MemToReg RegWr RegDst MemWr MemRd ALUctr ALUSrc ExtOp Reg. File Ext ALU S Mem Access M Data Mem Result Store Example Multicycle Datapath • Critical Path ? Equal nPC_sel E Reg File A IR PC Next PC B Instruction Fetch Operand Fetch

  17. Recall: Step-by-step Processor Design Step 1: ISA => Logical Register Transfers Step 2: Components of the Datapath Step 3: RTL + Components => Datapath Step 4: Datapath + Logical RTs => Physical RTs Step 5: Physical RTs => Control

  18. Time A S B M Step 4: R-rtype (add, sub, . . .) inst Logical Register Transfers ADDU R[rd]<–R[rs] + R[rt]; PC <– PC + 4 • Logical Register Transfer • Physical RegisterTransfers inst Physical Register Transfers IR <– MEM[pc] ADDU A<– R[rs]; B <– R[rt] S <– A + B R[rd] <– S; PC <– PC + 4 E Reg. File Reg File Exec IR PC Next PC Inst. Mem Mem Access Data Mem

  19. Time A S M Step 4: Logical immed inst Logical Register Transfers ORI R[rt] <– R[rs] OR ZExt(Im16); PC <– PC + 4 • Logical Register Transfer • Physical RegisterTransfers inst Physical Register Transfers IR <– MEM[pc] ORI A<– R[rs]; B <– R[rt] S <– A or ZExt(Im16) R[rt] <– S; PC <– PC + 4 E Reg. File Reg File Exec IR PC Inst. Mem Next PC B Mem Access Data Mem

  20. inst Physical Register Transfers IR <– MEM[pc] LW A<– R[rs]; B <– R[rt] S <– A + SExt(Im16) M <– MEM[S] R[rd] <– M; PC <– PC + 4 Time A S M Step 4 : Load inst Logical Register Transfers LW R[rt] <– MEM[R[rs] + SExt(Im16)]; PC <– PC + 4 • Logical Register Transfer • Physical RegisterTransfers E Reg. File Reg File Exec IR PC Inst. Mem Next PC B Mem Access Data Mem

  21. Time A S M Step 4 : Store inst Logical Register Transfers SW MEM[R[rs] + SExt(Im16)] <– R[rt]; PC <– PC + 4 • Logical Register Transfer • Physical RegisterTransfers inst Physical Register Transfers IR <– MEM[pc] SW A<– R[rs]; B <– R[rt] S <– A + SExt(Im16); MEM[S] <– B PC <– PC + 4 E Reg. File Reg File Exec IR PC Inst. Mem Next PC B Mem Access Data Mem

  22. Time S M Step 4 : Branch inst Logical Register Transfers BEQ if R[rs] == R[rt] then PC <= PC + 4+SExt(Im16) || 00 else PC <= PC + 4 • Logical Register Transfer • Physical RegisterTransfers inst Physical Register Transfers IR <– MEM[pc] BEQE<– (R[rs] = R[rt]) if E then PC<–PC+4+SExt(Im16)||00 else PC <–PC+4 E Reg. File Reg File A Exec PC IR Next PC Inst. Mem B Mem Access Data Mem

  23. Our Control Model • State specifies control points for Register Transfer • Transfer occurs upon exiting state (same falling edge) inputs (conditions) Next State Logic State X Register Transfer Control Points Control State Depends on Input Output Logic outputs (control points)

  24. Execute Memory Write-back Step 4  Control Specification for Multicycle Proc “instruction fetch” IR <= MEM[PC] “decode / operand fetch” A <= R[rs] B <= R[rt] LW R-type ORi SW BEQ PC <= Next(PC,Equal) S <= A fun B S <= A or ZX S <= A + SX S <= A + SX M<=MEM[S] MEM[S] <= B PC <= PC + 4 R[rd] <= S PC <= PC + 4 R[rt] <= S PC <= PC + 4 R[rt] <= M PC <= PC + 4

  25. Traditional FSM Controller next state control points state op cond Truth Table Next State control points 11 Equal 6 State 4 op datapath State

  26. Step 5  (datapath + state diagram control) • Translate RTs into control points • Assign states • Then go build the controller

  27. Execute Memory Write-back Mapping RTs to Control Points IR <= MEM[PC] “instruction fetch” imem_rd, IRen A <= R[rs] B <= R[rt] “decode” Aen, Ben, Een LW R-type ORi SW BEQ PC <= Next(PC,Equal) S <= A fun B S <= A or ZX S <= A + SX S <= A + SX ALUfun, Sen M <= MEM[S] MEM[S] <= B PC <= PC + 4 R[rd] <= S PC <= PC + 4 RegDst, RegWr, PCen R[rt] <= S PC <= PC + 4 R[rt] <= M PC <= PC + 4

  28. Execute Memory Write-back Assigning States “instruction fetch” IR <= MEM[PC] 0000 “decode” A <= R[rs] B <= R[rt] 0001 LW R-type ORi SW BEQ PC <= Next(PC) S <= A fun B S <= A or ZX S <= A + SX S <= A + SX 0100 0110 1000 1011 0011 M <= MEM[S] MEM[S] <= B PC <= PC + 4 1001 1100 R[rd] <= S PC <= PC + 4 R[rt] <= S PC <= PC + 4 R[rt] <= M PC <= PC + 4 0101 0111 1010

  29. (Mostly) Detailed Control Specification (missing0) State Op field Eq Next IR PC Ops Exec Mem Write-Back en sel A B E Ex Sr ALU S R W M M-R Wr Dst 0000 ?????? ? 0001 1 0001 BEQ x 0011 1 1 1 0001 R-type x 0100 1 1 1 0001 ORI x 0110 1 1 1 0001 LW x 1000 1 1 1 0001 SW x 1011 1 1 1 0011 xxxxxx 0 0000 1 0 x 0 x 0011 xxxxxx 1 0000 1 1 x 0 x 0100 xxxxxx x 0101 0 1 fun 1 0101 xxxxxx x 0000 1 0 0 1 1 0110 xxxxxx x 0111 0 0 or 1 0111 xxxxxx x 0000 1 0 0 1 0 1000 xxxxxx x 1001 1 0 add 1 1001 xxxxxx x 1010 1 0 1 1010 xxxxxx x 0000 1 0 1 1 0 1011 xxxxxx x 1100 1 0 add 1 1100 xxxxxx x 0000 1 0 0 1 0 -all same in Moore machine BEQ: R: ORi: LW: SW:

  30. Performance Evaluation • What is the average CPI? • State diagram gives CPI for each instruction type • Workload gives frequency of each type Type CPIi for type Frequency CPIi x freqIi Arith/Logic 4 40% 1.6 Load 5 30% 1.5 Store 4 10% 0.4 branch 3 20% 0.6 Average CPI: 4.1

  31. How Effectively are We Utilizing Our Hardware? IR <- Mem[PC] • Example: memory is used twice, at different times • Ave mem access per inst = 1 + Flw + Fsw ~ 1.3 • if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8 • We could reduce HW without hurting performance • extra control A <- R[rs]; B<– R[rt] S <– A + B S <– A or ZX S <– A + SX S <– A + SX M <– Mem[S] Mem[S] <- B R[rd] <– S; PC <– PC+4; R[rt] <– S; PC <– PC+4; R[rd] <– M; PC <– PC+4; PC <– PC+4; PC < PC+4; PC < PC+SX;

  32. “Princeton” Organization A-Bus B Bus • Single memory for instruction and data access • Memory utilization -> 1.3/4.8 • Sometimes, muxes replaced with tri-state buses • Difference often depends on whether buses are internal to chip (muxes) or external (tri-state) • In this case our state diagram does not change • Several additional control signals • Must ensure each bus is only driven by one source on each cycle A Reg File next PC P C I R S Mem B ZX SX W-Bus

  33. Another Alternative MultiCycle DataPath A-Bus • In each clock cycle, each Bus can be used to transfer from one source • µ-instruction can simply contain B-Bus and W-Dst fields B Bus A Reg File next PC P C inst mem I R mem S B ZX SX W-Bus

  34. What about a 2-Bus Microarchitecture (datapath)? Instruction Fetch A-Bus B Bus A Reg File next PC P C I R S Mem M B ZX SX Decode / Operand Fetch A Reg File next PC P C I R S Mem M B ZX SX

  35. Load Execute • What about 1 bus ? 1 adder? 1 Register port? A Reg File next PC P C I R S Mem M B ZX SX Mem addr A Reg File next PC P C I R S Mem M B ZX SX Write-back A Reg File next PC P C I R S Mem M B ZX SX

  36. Summary • Disadvantages of the Single Cycle Processor • Long cycle time • Cycle time is too long for all instructions except the Load • Multiple Cycle Processor: • Divide the instructions into smaller steps • Execute each step (instead of the entire instruction) in one cycle • Partition datapath into equal size chunks to minimize cycle time • ~10 levels of logic between latches • Follow same 5-step method for designing “real” processor

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