EECE **** Embedded System Design

1. EECE **** Embedded System Design

2. Memory • For the memory, efficiency is again a concern: • speed (latency and throughput); predictable timing • energy efficiency • size • cost • other attributes (volatile vs. persistent, etc) Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

3. Access times and energy consumption increases with the size of the memory "Currently, the size of some applications is doubling every 10 months" Example (CACTI Model): Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

4. Area (l2x106) Power (W) Cycle Time (ns) Access times and energy consumptionfor multi-ported register files • Rixner’s et al. model [HPCA’00], Technology of 0.18 mm Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

5. Reducing energy consumption with Sub-banking • shorter wires, • lower capacitances, • faster access Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

6. Mobile PC Average System Power Mobile PC Thermal Design (TDP) System Power Other 600/500 MHz uP 600/500 MHz uP Other 13% 37% 13% 13% Power Supply Power Supply 10% 10% Memory+Graphics LCD 10" 12% Memory+Graphics 30% 15% HDD LCD 10" 9% HDD 19% 19% Note: Based on Actual Measurements Multiple Platform Components Comprise Average Power CPU Dominates Thermal Design Power How much of the energy consumption of a system is memory-related? Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

7. „CPU“ Power Dissipation 42%/40% again memory-related ! IEEE Journal of SSC Nov. 96 Proceedings of ISSCC 94 Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

8. Speed 8 CPU (1.5-2 p.a.) 4  2x every 2 years 2 DRAM (1.07 p.a.) 1 years 0 1 2 3 4 5 Access-times will be a problem • Speed gap between processor and main DRAM increases • early 60ties (Atlas):page fault ~ 2500 instructions • 2002 (2 GHz µP):access to DRAM ~ 500 instructions •  penalty for cache miss about same as for page fault in Atlas Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

9. Predictability is a problem (1) • Embedded system systems are often real-time systems: • Have to guarantee meeting timing constraints. • Predictability: For satisfying timing constraints in hard real-time systems, predictability is the most important concern;pre run-time scheduling is often the only practical means of providing predictability in a complex system [Xu, Parnas] Time-triggered, statically scheduled operating systems Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

10. Predictability is a problem (2) • Currently available caches don‘t solve the problem: • Improve the average case behavior • Use „non-deterministic“ cache replacement algorithms Scratch-pad/tightly coupled memory based predictability Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

11. main SPM processor 0 scratch pad memory ARM7TDMI cores, well-known for low power consumption FFF.. Hierarchical memoriesusing scratch pad memories (SPM) • Address space Hierarchy Example no tag memory Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

12. Comparison of currents using measurements E.g.: ATMEL board with ARM7TDMI andext. SRAM /3 Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

13. € Comparison of energy consumption Example: Atmel ARM-Evaluation board Main memory access takes more cyclessavings (86%) larger than for current. energy reduction:/ 7.06 Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

14. Why not just use a cache ? • Predictability? Worst case execution time (WCET) may be large Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

15. Why not just use a cache ? (2) • Energy for parallel access of sets, in comparators, muxes. Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

16. Influence of the associativity Parameters different from previous slides Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

17. Flash Memory Based on EPROM/EEPROM-Memory EPROM storage cell Row (j) FG charged FG not charged Ground Read amplifier floating gate FG can be charged by high voltage. Charged transistor non-conducting if row selected. Discharging with UV light. Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

18. Row (j) FG charged FG not charged Ground EEPROMS storage cell EEPROM= electrically erasable read only memory. EEPROM needs additional transistor per bit Writing and erasing requires just electrical signals Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

19. NOR- and NAND-Flash • NOR: Transistor between bit line and ground • NAND: Several transistor between bit line and ground contact contact Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science

20. Properties of NOR- and NAND-Flash memories Department of Electrical and Computer Engineering College of Engineering, Technology and Computer Science