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Reconfigurable Computing - VHDLPowerPoint Presentation

Reconfigurable Computing - VHDL

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Reconfigurable Computing - VHDL. John Morris Computer Science/ Electrical and Computer Engineering The University of Auckland. Iolanthe racing off Fremantle, Western Australia. Resources. These notes Will be available on the Web

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### Reconfigurable Computing -VHDL

John Morris

Computer Science/

Electrical and Computer Engineering

The University of Auckland

Iolanthe racing off Fremantle,Western Australia

Resources

- These notes
- Will be available on the Web
- You can download them fromhttp://cs.auckland.ac.nz/~jmor159/reconfig

- Other resources
- Links will be available on the same web site

- VHDL text
- Any text on VHDL will be adequate!
- RecommendedP J Ashenden, Designer’s Guide to VHDL(A fellow Australian!)
- Ashenden’s other text andseveral other suitable texts in the library

Background

- US Department of Defense ‘High Order Language’ project
- Aim: One language for all defense needs
- Result: Ada

- Ada
- General purpose programming language
- Based on Pascal
- Original Ada was not Object-Oriented
- Ada’95 has OO capabilities
- Named after Ada, Countess of Lovelace
- Never write it as ADA – it’s not an acronym!
but VHDL is one!

- Never write it as ADA – it’s not an acronym!

VHDL

- VHSIC Hardware Design Language
- VHSIC = Very High Speed Integrated Circuit

- Standardized; mature
- IEEE 1076-2002
- IEEE 1076-1987 (VHDL’87)
- IEEE 1076-1993 (VHDL’93)
- Several associated standards
- IEEE.std_logic
- IEEE.numeric_std

- Based on Ada
- Extensions added to support Hardware Design
- VHDL compiler should accept simple Ada programs
- Ada compiler should accept VHDL functions

- About half of all high-level electronic design uses VHDL
- Remainder is Verilog (C based)
- Verilog did not become a standard until 1995 and was revised in 2001 (IEEE1364-2001)

VHDL - Basics

- Case insensitive
- Convention
- Keywords in upper case
- BEGIN, END, ENTITY, ARCHITECTURE, LOOP, ….

- Variables in lower case
- i, j, k, clock, …

- Types in lower case
- integer, std_logic, std_logic_vector

- This is just a convention – you can choose your own!

- Keywords in upper case
- For these slides, I will use this font and colour
- ENTITY adder IS …

- Convention
- for anything that you could type into a VHDL model

Assignment operator is :=

Statement terminated by ;

VHDL - Basics- Statements similar to Pascal
- Variable declaration
- x, y : integer;

- Assigment
- x := 5.0*y + 2;

- Program blocks delimited by BEGIN … END;
- Example

- Variable declaration

- PROCEDURE SQR( x: integer ) RETURNS integer IS VARIABLE z : integer; BEGIN
- z := x * x;
- RETURN z; END;

VHDL is quite verbose

(long winded!)

VHDL – Entities and Architectures

- VHDL supports abstraction through
- Entities
- Defines interface for a module

- Architectures
- Implementation of a module
- There may be several architectures corresponding to one entity
- Generally, there are several ways (circuits) that will produce the same result

- Entities

8

8

VHDL – Entities- Example: n-bit adder

ENTITY adder IS PORT ( a, b : IN std_logic_vector; sum : OUT std_logic_vector; carry_out : OUT std_logic; );END adder;

adder

sum

a

b

carry_out

There are several ways of

Implementing an n-bit adder

… but all have the same interfaceor ENTITY in VHDL

Architectures

- An architecture contains the implementation details
- At a high level, a designer is only interested in the interface – information contained in the VHDL ENTITY
- Each ARCHITECTURE is associated with an ENTITY

ARCHITECTURE ripple OF adder IS …END ripple;

ENTITY adder IS PORT ( … );END adder;

One or more architectures

ARCHITECTURE c_select OF adder IS …END c_select;

One entity

Architecture – Style

- Styles of architecture
- You can design a circuit in several ways
- In VHDL, you can build a model for a circuit in several ways too!
- Behavioural
- Dataflow
- Algorithmic

- Structural

- Behavioural

1

1

1

1

Architectures – Style example- Example
- Consider a full adder:
- Logic equations are:

ENTITY full_adder IS PORT (

a, b : IN std_logic; sum : OUT std_logic; carry_out : OUT std_logic;

);END adder;

adder

a

sum

b

carry_out

c_in

sum := a xor b xor c;

carry_out := (a and b) or (b and c) or (a and c);

1

1

1

1

Architectures – Dataflow style- Example
- Consider a full adder:
- Logic equations are:
- Dataflow architecture is

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

adder

a

sum

b

carry_out

c_in

sum := a xor b xor c;

carry_out := (a and b) or (b and c) or (a and c);

a

sum

b

carry_out

c_in

Note that these are signal assignments.

Although they are similar to ordinary assignments (using :=),there are some important differences which we will consider soon!

1

1

1

1

1

Architectures – Behavioural (Dataflow ) style- Example
- Consider a full adder:
- Logic equations are:
- Dataflow architecture is

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

sum := a xor b xor c;

carry_out := (a and b) or (b and c) or (a and c);

ARCHITECTURE df OF full_adder IS BEGIN

sum <= a xor b xor c;

carry_out <= (a and b) or (b and c) or (a and c);

END df;

a

sum

b

carry_out

c_in

1

1

1

1

1

Architectures – Structural style- Example
- Consider a full adder:
- Logic equations are:
- A Structural model builds a model from other models

ENTITY full_adder IS a, b : IN std_logic; sum, carry_out : OUT std_logic;END full_adder;

sum := a xor b xor c;

carry_out := (a and b) or (b and c) or (a and c);

Architectures – Structural style

ENTITY xor IS a, b : IN std_logic; c : OUT std_logic;END xor;

- Build basic models for internal elements:
- xor
- or
- and

- Build the full adder from these elements

ENTITY or IS a, b : IN std_logic; c : OUT std_logic;END xor;

ENTITY and IS a, b : IN std_logic; c : OUT std_logic;END xor;

Architectures – Structural style

- Build basic models for internal elements:
- xor
- or
- and

- For these, the architecturesare trivial

ENTITY xor IS a, b : IN std_logic; c : OUT std_logic;END xor;

ARCHITECTURE A OF xor IS c <= a xor b; END xor;

x2

Map the signals in xor’s ENTITYto actual wires in this circuit

Instantiate an xor circuit, label it x1

Instantiate a second xor circuit, label it x2

Architectures – Structural style- Now you ‘wire up’the basic elementsto make the full adder circuit
- Considering the sum part only

ab

a

b

sum

c

ARCHITECTURE structural OF full_adder IS SIGNAL ab: std_logic;

BEGIN

x1: xor PORT MAP( a => a, b => b, c => ab );

x2: xor PORT MAP( a => ab, b => c, c => sum );

… -- or / and circuits to compute carry out

END structural;

Architectures – Algorithmic style & mixtures

- Algorithmic models can include any type of construct that you find in a high level language – if … then … else, case, loop, procedure calls, etc.
- We will look at some examples of this style after we’ve reviewed VHDL statements

- Note that styles can be mixed in one model
- A structural style model may include some dataflow statements and some algorithmic blocks, etc.

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