1 / 21

D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP

D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP. Magnus Själander. Contents. Double Data Rate Interfaces DDR SDRAM Architecture and Functionality DDR Memory Controller Data Resynchronization Floorplan and Place & Route Future Work Conclusion.

loring
Download Presentation

D ESIGN AND I MPLEMENTAION OF A DDR SDRAM C ONTROLLER FOR S YSTEM ON C HIP

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. DESIGN AND IMPLEMENTAION OF ADDR SDRAMCONTROLLERFOR SYSTEM ON CHIP Magnus Själander

  2. Contents • Double Data Rate Interfaces • DDR SDRAM Architecture and Functionality • DDR Memory Controller • Data Resynchronization • Floorplan and Place & Route • Future Work • Conclusion

  3. Double Data Rate Interfaces New • Data Transmissions on rising and falling edge • Data Strobe Advantages • Time of Flight • Clock Skew • Pin Count • Bandwidth Disadvantage • Synchronization

  4. SDRAM Architecture • Four Banks • Row and Column Select Lines • 1T Memory Cells • Sense Amplifiers • Global Data Path

  5. DDR SDRAM Architecture • 2n-prefetch • Delay Lock Loop

  6. DDR SDRAM Improvements • Long Delay in Column Decode and Data Lines • Added a Delay Lock Loop to Increase Clock Frequency

  7. DDR SDRAM Commands Same Commands as for Standard SDRAM • READ • WRITE • ACTIVATE • PRECHARGE • REFRESH • MRS (Mode Register Set) Added • EMRS (Extended MRS)

  8. DDR SDRAM Memory Controller

  9. Core Memory Controller

  10. AHB Interface

  11. Arbiter

  12. Capturing the Data • Phase Shift the Data Strobe • Resynchronize the Data

  13. Phase Shift the Data Strobe • Delay Lock Loop • Inverter Delay • PCB Line Delay • Programmable Delay Line with Temperature Sensing

  14. Synchronization of the Data One Flip-Flop for each Flank to Sample

  15. Synchronization of the Data Continued

  16. Synchronization of the Data Continued Simplified Phase Detector

  17. Floorplan

  18. Place & Route

  19. Future Work • Improved Refresh Handling • Attempt to Reduce Initial Latency for Bursts • Improved Buffer Handling

  20. Conclusion • Working Implementation • Smaller Changes to Improve Performance • Highlights Difficulties and Solutions

  21. Questions ?

More Related