Area-reducing Sharing of Mutually Exclusive Multiplier, MAC, Adder and Subtractor blocks

1. Area-reducing Sharing of Mutually Exclusive Multiplier, MAC, Adder and Subtractor blocks Sabyasachi Das Synplicity Inc Sunil P. Khatri Texas A&M University

2. The Problem Statement e k g h c d f b a • This is an example of a generalized sharing problem involving multiple arithmetic Sum-of-Product blocks • Goal: Design a shared area-efficient architecture q = c * d + e r = f + g p = a * b t = h - k t r q p s0 4-to-1 MUX s1 z

3. e d f b c a q = c * d p = a * b q p z = p + q + e + f z What is a Sum-of-Product? • IC block that performs addition of multiple product and sum terms • Computationally-intensive • Consumes large area • Wide usage in DSP, Graphics, Microprocessors

4. Multiplication {assign z = a * b} MAC {assign z = (a * b) + c} 2-operand Addition {assign z = a + b} Squarer {assign z = a * a} Adder-Tree {assign z = a + b + c + d} Generalized SOP {assign z = (a * b) + (c * d) + (e * f) + g + h + k} Examples of Sum-of-Product Blocks

5. Structure of Sum-of-Products Inputs • Sum-of-Products block consists of 3 parts (written in the order of data-flow) • Partial Product Generator (PPGen) • Partial Product Reduction Tree (PPRT) • Final Carry-Propagation Adder (CPA) Partial Product Generator (PPGen) Partial Product Reduction Tree (PPRT) Final Carry Propagation Adder (CPA) Output

6. PPGen for one Product in an SOP a3 a2 a1 a0 * b3 b2 b1 b0 a3b0 a2b0 a1b0 a0b0 a3b1 a2b1 a1b1 a0b1 a3b2 a2b2 a1b2 a0b2 a3b3 a2b3 a1b3 a0b3 PPGen of each Product-term in an SOP generates its own partial product vectors

7. PPRT and CPA (a*b) + (c * d) + e +f _________________________ a3b0 a2b0 a1b0 a0b0 a3b1 a2b1 a1b1 a0b1 … … … c3d0 c2d0 c1d0 c0d0 c3d1 c2d1 c1d1 c0d1 … … … e3 e2 e1 e0 f3 f2 f1 f0 _________________________ … … … x5 x4 x3 x2 x1 x0 … … … y5 y4 y3 y2 y1 y0 • All partial products (from product and sum terms) are combined together • Single PPRT reduces these to two vectors • Final Adder (CPA) adds to produce the output

8. Our Proposed Approach • Identify the similarity between all the operations • Identify the largest SOP block among all involved blocks • Implement the largest block • Reuse different parts of the largest block (with MUXes) to implement other smaller SOP blocks

9. Adder and Subtractor • Adder and Subtractor are similar operations b Inv b a a b z = a - b z = a + b 1’b1 z z

10. MAC and Multiplier • MAC and Multiplier are similar operations • Both contain PPGen, PPRT, CPA • Both are specific cases of SOP • For a Multiplier (a*b) with n-bit wide input signals, there are n rows of partial products • For a MAC (c*d+e) with n-bit wide input signals, there are (n+1) rows of partial products

11. a c k g h b e d f Inverter s0 M1 M2 N’b0 s0 M5 s0 M4 M3 PPGen M7 s1 M6 PPRT s0 CPA s1 z Proposed Approach of Sharing • Each of the 4 operations are specific examples of generalized Sum-of-Products • Implement the shared architecture with MUXes

12. Results On an average, 34.5%smaller than the result of the commercial Datapath Synthesis tool

13. Results e g h c d const f b a • If most or all the blocks have similar complexity (like, Multiplier, MAC, Squarer, Constant-Mult), that will result in more area savings (as high as 55%-60% area savings in this new example). q = c * d + e r = f * g p = a * b t = h * const t r q p s0 4-to-1 MUX s1 z

14. Results c b a a b const a b a • If most or all the blocks have same input signals, that will result in more area savings (as high as 60%-70% area savings in this new example). q = a * b + c r = a * b p = a * b t = a * const t r q p s0 4-to-1 MUX s1 z

15. Inputs Inputs Inputs SOP1 SOP2 SOP7 . . . . . . t p q s0 8-to-1 MUX s1 s2 z Results • If there are more mutually exclusive SOP blocks, that will result in more area savings (as high as 70%-80% area savings in this new example of 8 similar SOPs).

16. Thank you