Extending and Expanding Moore’s Law— Challenges and Opportunities

1. Extending and Expanding Moore’s Law—Challenges and Opportunities Shekhar Borkar Intel Corp. Aug 29, 2006

2. Outline • Today’s challenge: Power • Evolution of Multi—everywhere • What’s beyond Multi—? • Future challenges: variations and reliability • Resiliency • Summary

3. How do you get there? Goal: 10 TIPS by 2015 Pentium® 4 Architecture Pentium® Pro Architecture Pentium® Architecture 486 386 286 8086

4. Technology, Circuits, and Architecture to constrain the power Power is the Challenge! ) 1400 2 SiO2 Lkg 10 mm Die 1200 SD Lkg Active 1000 800 Power (W), Power Density (W/cm 600 400 200 0 90nm 65nm 45nm 32nm 22nm 16nm

5. Near Term Solutions • Move away from Frequency alone to deliver performance • More on-die memory • Multi-everywhere • Multi-threading • Chip level multi-processing • Throughput oriented designs • Valued performance by higher level of integration • Monolithic & Polylithic

6. Multi-threading Increase on-die Memory C1 C2 Large Core Cache Single Thread C3 C4 Improved performance, no impact on thermals & power delivery Full HW Utilization Wait for Mem ST Multi-Threading Chip Multi-processing Wait for Mem MT1 Wait MT2 MT3 mArchitecture Techniques

7. Cache Large Core Small Core C1 C2 Cache C3 C4 Multi-Core Power Power = 1/4 4 Performance Performance = 1/2 3 2 2 1 1 1 1 4 4 Multi-Core: Power efficient Better power and thermal management 3 3 2 2 1 1

8. Source: Mark Bohr, Intel Lithography Wavelength 365nm 248nm 193nm 180nm 130nm 90nm Gap 65nm 45nm Generation 32nm 13nm EUV Random Dopant Fluctuations Sub-wavelength Lithography Heat Flux (W/cm2)—Vcc variation Temp Variation & Hot spots Sources of Variations

9. Impact of Static Variations Today… 1.4 Frequency ~30% Leakage Power ~5-10X 30% 1.3 1.2 130nm Normalized Frequency 1.1 1.0 5X 0.9 1 2 3 4 5 Normalized Leakage (Isb)

10. Vdd Vdd Ip Op Op Vss Vss Today’s Freelance Layout No layout restrictions

11. Vdd Vdd Ip Op Op Vss Vss Transistor Orientation Restrictions Transistor orientation restricted to improve manufacturing control

12. Transistor Width Quantization Vdd Vdd Op Ip Op Vss Vss

13. Today’s Unrestricted Routing

14. Future Metal Restrictions

15. Implications to Design • Design fabric will be Regular • Will look like Sea-of-transistors interconnected with regular interconnect fabric • Shift in the design efficiency metric • From Transistor Density to Balanced Design • Interconnect RC not a major issue • Benefits of custom design (performance, density) will diminish

16. Technology Outlook

17. Wider Extreme device variations Soft Error FIT/Chip (Logic & Mem) Burn-in may phase out…? Time dependent device degradation Reliability

18. Implications to Reliability • Extreme variations (Static & Dynamic) will result in unreliable components • Impossible to design reliable system as we know today • Transient errors (Soft Errors) • Gradual errors (Variations) • Time dependent (Degradation) Reliable systems with unreliable components —Resilient mArchitectures

19. Implications to Test • One-time-factory testing will be out • Burn-in to catch chip infant-mortality will not be practical • Test HW will be part of the design • Dynamically self-test, detect errors, reconfigure, & adapt

20. 100 Billion Transistors 100 BT integration capacity Billions unusable (variations) Some will fail over time Intermittent failures In a Nut-shell… Yet, deliver high performance in the power & cost envelope

21. Summary • Moore’s Law is alive and well • Multi— is the key solution • Many and too many cores, longer term • Not just for power and performance • But to deliver highest performance in the power envelope with resiliency Reliable Systems with Unreliable Components