Instrument Data Processing Unit (IDPU)

1. Instrument Data Processing Unit(IDPU) Michael Ludlam Space Sciences Lab University of California, Berkeley

2. IDPU Introduction Requirements Block Diagram Board Overview Specifications Heritage Spacecraft & Inter-board Interfaces Backplane Shielding Resources I&T Schedule Personnel

3. IDPU Introduction Scope of Presentation Gives overview of Instrument Data Processing Unit (IDPU). Areas that are handled at the IDPU top level are discussed in detail here. Individual board details, requirements and designs are discussed during those board presentations. Synopsis: IDPU houses most of the instrument electronics, providing the electrical interface between the spacecraft and the sensor / boom units. It contains four circuit boards: Low Voltage Power Supply (LVPS) and Power Control Board Circuit (PCB) Digital Control Board (DCB) Digital Fields Board (DFB) Boom Electronics Board (BEB)

4. IDPU Requirements Requirements for IDPU are derived from the EFW System Requirements (RBSP_EFW_SYS_001_Requirements) Only requirements that are directly relevant to the IDPU as a unit are reported here. Individual board level requirements are detailed in appropriate presentations.

5. IDPU Block Diagram

6. IDPU Board Overview IDPU Contains 4 Boards: LVPS & PCB (SSL) – Power supply and switching. Receives power from S/C and converts it to board required voltages. Converters all synchronized together from one frequency (799 kHz). Boom deployment voltages are S/C provided but switched on the PCB circuit. DCB (SSL) – Processor Board, Memory and S/C Digital Interface. Accepts and responds to incoming S/C commands and sends Housekeeping and compressed Science Data in Telemetry stream. On card memory stores data received from DFB. DFB (LASP) – Analog and Digital Signal Processing. Processes signals from sensors and digitizes them to produce waveform and spectral products that are sent to the DCB board. BEB (SSL) – Boom Sensor Control. Supplies bias current and control voltages to set the sensors to the correct operating regime.

7. IDPU Electrical Specifications Board Specification Documents: RBSP_EFW_LVPS_001J_Specification RBSP_EFW_DCB_003E_Specification RBSP_EFW_DFB_001D_SPECrevD_07_29_09.pdf RBSP_EFW_BEB_001G_Specification RBSP_EFW_BPL_001M_Specification

8. IDPU Heritage RBSP IDPU is heavily based on the successful THEMIS IDPU, failure free on-orbit combined operation for over 13 spacecraft-years. The THEMIS IDPU itself was based on a long history of instrumentation at SSL/UCB. Themis IDPU

9. IDPU External Electrical Interfaces IDPU provides interface to S/C via: 1 x 15M DSub Connector on the LVPS (Instrument and Boom Deploy Power). 1 x 9F DSub Connector on the DCB (Instrument Commands, 1PPS/SP, Instrument Telemetry). Interfaces are defined in the APL Controlled EFW ICD (7417-9083) – currently RevA. LVDS has been verified by APL provided GSE. ETU IDPU Test planned at APL. S/C Model power switch circuit from EMECP has been built up for testing with the LVPS. IDPU provides interface to boom units via: 3 x 26F HDSub Connectors on the BEB board (Defined in BEB Specification – RBSP_EFW_BEB_001). 1 x 62F HDSub Connector on the LVPS/PCB board (Defined in LVPS/PCB Specification – RBSP_EFW_LVPS_001). Verified during instrument I&T Safe-to-Mate. IDPU provides interface to EMFISIS via: pins on 3 x 26F HDSub Connectors on BEB Board (EFW out). 1 x 26M HDSub Connector on DFB (MAG, MSC in). Interfaces are defined in the APL Controlled EFW to EMFISIS ICD (7417-9089) –currently RevA. Verified by EFW – EMFISIS interface test on ETU (August 09).

10. IDPU Internal Electrical Interfaces IDPU Boards plug into a backplane board that provides board to board connections – power, command, telemetry, and housekeeping. Digital board to board interfaces are: DCB – DFB : UCB ‘CDI’ interface – serial data protocol for command and telemetry using a common clock. DCB – BEB : Controls DACs via command, clock and latch lines, muxes with bi-level control signals, test signal (AC Test) – 2 lines. DCB – PCB : Command, Clock and Strobe line control decoders on PCB circuit. Change from I-PDR – unused connections are removed from connectors. Initial board-to-board tests use a GSE backplane that is mounted in a standard VME 19” rack.

11. Change to KA Series Connector Original backplane design used AVX DIN96 style connectors for the BEB, DFB, DCB, that used the bifurcated design that is no longer allowed by NASA. Changed to Hypertronics KA series in April 09. New connectors are from same family as part used on THEMIS and RBSP LVPS. Parts are in house and in use on BEB and DFB ETU2’s (second version of ETUs). Connectors are good to 300V after derating. Maximum voltage is 240V.

12. Backplane Layout ETU IDPU uses old DIN96 connector. IDPU Flight Backplane layout using the new KA98 Hypertroncis connectors is complete. Board to be built with FR4 (4101/26) GSE board to board tests use a GSE backplane that is mounted in a standard VME 19” rack, that accommodates both the old DIN96 connectors (for GSE) and the new KA98 series connector.

13. Shielding EMC/EMI board shields on the LVPS, DCB and DFB. No radiation spot shielding on any IDPU board – radiation shielding is done at box level (covered by IDPU Mechanical Design presentation). BEB Board DFB Shield DCB Shield LVPS Shield

14. IDPU Power • All power for EFW is routed through the IDPU, including that to deploy booms. • The supplies for the IDPU (PCB, DCB and DFB) and the BEB are independent allowing the BEB to function in the event of failure on another IDPU board and continue to provide EMFISIS with E-field sensor signals. • Average power increased by 1.4 W since CBE at IPDR. • Most of this increase is due to the actual versus predicted efficiency of the supply. • Still under NTE, but straightforward adjustments to design expected to improve efficiency, and thus margin. Average Power

15. Mass Resources IDPU Mass is 8.20kg (CBE) and has a NTE of 9.73kg (19% margin) IDPU board mass are ETU measured and are not expected to change significantly – although flight boards once staked and coated are likely to be 50 to 100 g heavier. Chassis mass will be covered by IDPU Chassis presentation. CBE Mass

16. ETU Testing DFB, DCB and BEB boards were integrated together in April / May 2009. LVPS integrated into IDPU in early August 2009, in time for interface tests with EMFISIS in mid-August 2009(see I&T presentation). Interfaces between boards worked well, and there are no modifications to the interface for flight. Further IDPU testing involving SPB/AXB deployment and LVPS/BEB Thermal testing is due to occur in September/October 09.

17. Subsystem Testing Flight IDPU I&T Flow: Individual IDPU boards delivered to IDPU for integration once they have met board requirements and completed test procedures. Board-to-board interfaces are then verified (safe-to-mate). Integration follows written test procedures. Unit is assembled in box and functionally tested (CPT). IDPU then supports SPB/AXB testing (deployments / functionals). IDPU boards are staked and coated. IDPU then ready for remaining I&T / environments. Further I&T descriptions are dealt in I&T presentation.

18. Schedule IDPU Schedule is kept up to date and reported monthly. Key Dates: ETU IDPU delivery to I&T: August 2009 F1 IDPU delivery to I&T: March 2010 F1 Instrument I&T: June 2010 F2 IDPU delivery to I&T: April 2010 F2 Instrument I&T: July 2010

19. Data Control Board (DCB) Michael Ludlam Space Sciences Lab University of California, Berkeley

20. Data Control Board Introduction Requirements Block Diagram Specification Board Overview Design Interfaces Heritage Resources Breadboard ETU Parts Schedule RBSP DCB ETU

21. DCB Introduction Scope of Presentation Gives overview of DCB board. DCB FPGA Actel presentation follows and is only presented as a component in this presentation. EFW FSW is detailed in a separate presentation. Synopsis -- The DCB card: provides the digital interface between the S/C and the rest of the instrument. receives, packetizes and stores science data before transmitting it to the spacecraft. receives and transmits housekeeping to the spacecraft. receives and acts on commands from the spacecraft.

22. Board Overview & Requirements

23. ETU Board

24. FPGA & FSW Requirements EFW requirements are flowed to subsystems and also used to derive FSW requirements. RBSP_EFW_FSW_002D FPGA requirements are flowed from the DCB board into the DCB FPGA specification. Both the DCB Board and DCB FPGA specification are reviewed for completeness by the Systems Engineer, the FSW Engineer, the DCB Engineer and the DCB FPGA Engineer.

25. Changes since PDR No changes to requirements since PDR for DCB board. No major component changes since PDR.

26. EFW Block Diagram

27. DCB Block Diagram

28. DCB Specifications DCB Board Specification Document: RBSP_EFW_DCB_003E_Specification DCB FPGA Specification Document: RBSP_EFW_DCB_001N FSW Specification Document: RBSP_EFW_FSW_003_Specification Mechanical ICD: RBSP-IDP-MEC-011 Rev F

29. Interfaces DCB has digital interface to S/C via 9F DSub Connector (Instrument Commands, 1PPS/SP, Instrument Telemetry). Interface is defined in the APL Controlled EFW ICD (7417-9083) –currently RevA. Signal levels have been verified by APL provided Emulator. Test planned with ETU IDPU at APL. DCB also has an external 51-pin connector to debug board. Connector cover will be installed on delivery of FM IDPUs to APL. Board built for ETU that allows alternative boot PROM / EEPROM and logic analyzer connections. Will be used on flight board until flight PROM is burned and installed. Internal IDPU communications are routed on the 98-pin KA connector that connects to the backplane. Verified during integration with other IDPU boards. No issues found during ETU testing. S/C Debug / Alternative Boot Backplane

30. Heritage Heritage DCB is based on THEMIS equivalent board (also called the DCB). Although processor is different (RBSP: Z80, THEMIS: 8085) instruction set is compatible and allows reuse of FSW modules. SDRAM, ADC and MUX is identical to one flown on THEMIS. SRAM, EEPROM are 3.3V equivalent parts of those flown on THEMIS. New for RBSP! IP Core – Extensively tested on ETU. Flash – Extensively tested on ETU. LVDS – Extensively tested on ETU, APL recommended parts. MSK Regulator for 1.5V and 3.3V supplies. Extensively tested on ETU. RTAX FPGA – Not yet tested.

31. Resources Mass CBE 543g, NTE 586g. Power CBE 1.24W, NTE 2.09W.

32. Radiation All DCB Active parts are rad-hard/rad-tolerant or have undergone a TID test. (Board designed to TID of 33-kRad(Si).) All DCB Active parts are SEL immune up to 80 MeV/cm2 or have a waiver. Parts with waiver: LTC1604 (ADC) Flash memory Parts on S/C interface have been tested by APL for DDD.

33. ETU Testing Results • Board tested to and met requirements. • Board has supported FSW, FPGA and IDPU testing without problems. • No major modifications have been necessary to the board. • One potential issue arose with the MSK regulator parts which require a large (0.5-A) start up current. ETU Testing with the LVPS shows the power supply is able to support this. A more flight-like load test is planned in September 09.

34. DCB Flight Layout • Flight layout has been started and will be completed in early October 2009. • Minor Changes from ETU: • Buffers run as warm spare for the Flash & SDRAM. • Changed DIN96 connector to the new KA98 connector. • Removal of filter on regulator supplies (no longer necessary after SEU testing of parts). • Corrected switch to SDRAM and Flash • Minor changes to layout to correct layout errors • Added buffer enable control to the Flash to FPGA • Added Analog Spare nets to connector for spares. • Differences between ETU and Flight: • FPGA on ETU board is Aldec adaptor board with A3P1500 part. • Oscillator is commercial part. • Other parts are engineering versions of flight parts. • Board will be manufactured from FR4 (4101/26) • Still to be done: • Minor tweaks of signal trace impedances. • Power Control Board (PCB) interface circuitry checkout

35. Test Plan Test plan was written for ETU testing – RBSP_EFW_DCB_004 Prior to FPGA installation Simple Power Up POR Oscillator check After FPGA installation Verification of signal integrity on board & board timing. This will be developed into a test procedure for the flight board and run on the ETU first. Once the board is populated and delivered to UCB, functionality that can be checked at a hardware only level will be verified, before handing over to FPGA verification and FSW verification. Both flight boards will be assembled together. FPGA will be installed on one board and tested before second board has FPGA installed.

36. Peer Review AI

37. IC Parts List & Status All long lead parts are in house or due soon. All parts meet derating defined in INST-002. Although team has extensive experience with Actel parts, we have not yet programmed and run a RTAX part. All other parts have been tested using ETU version or have recent flight history (THEMIS).

38. Handling Flight boards will be assembled by approved external contractor (Jackson and Tull). Board handled with gloves / ESD strap at all times during functional checkout / board verification. After functional tests are complete the board will be cleaned before being staked and coated. Board then only unbagged in cleanroom.

39. Schedule Board is ready for flight. Board layout and fabrication due to happen in October 2009 Assembly in November 2009 Test in December 2009 DCB progress is tracked in the IDPU Schedule.

40. This page intentionally almost blank