A brief overview of the ATLAS Pixel Detector. Overview. It will (try) to give a brief overview over the layout, components and status of the Atlas Pixel system Layout Modules Sensors and chip Staves Support structure and integration
NIEL > 1015 1 MeV neq/cm2
Operates inside the 2T field
Cooled by C3F8 evaporative system . Environmental temperature kept below 0C.
Module Controller Chip
16 FE chips
The front-electronics chip, FE-I3, is built in 0.25 m IBM technology:
Each chip reads out 2880 pixels (7.4x11mm die). Each pixel cell consists of a fast preamplifier followed by a discriminator
sparse readout and store hits in EndOfColumn buffers until the level 1 trigger is received
Threshold can be adjusted by a 7-bit tuning DAC in each channel.
8-bit pulse height information is obtained by the Time-over-Threshold technique. ToT uniformity is obtained by a 3-bit tuning DAC
On wafer testing measured yield is 81%
Production finished ( >45000 chip)
AMS - In
IZM – PbSn
In-time efficiency as function of
Time -> plateau of 10ns width
ToT for 1 pixel
Module production is almost finished: need is 1744 modules
Production yield is ~ 93%
Modules are ranked to install the best on the B-layer and disk1, ranking =60 0.1% of dead pixel
Status as of May 2006
(1/8 of a disk):
6 modules are mounted on carbon-carbon plates, sandwiching the cooling pipe.
All 6 disks have been assembled in LBL and ENDCAP C is now at CERN
Will be used for a first commissioning of the Pixel Detector using a cosmic setup in SR1
A 3 hit Pixel Detector is on its way to record LHC events in ATLAS
Oxygenated FZ silicon was chosen
because of improved hardness
to charge particle irradiation.
No. of transistors: 880 k
Dimensions: 6840 x 5140 mm2