One Gigasample Per Second Data Acquisition Using Available Gate Array Technology

1. One Gigasample Per Second Data AcquisitionUsing Available Gate Array Technology Kenneth W. Wagner Computer Engineer Microelectronics and Signal Processing Branch -- Code 564 NASA Goddard Space Flight Center Greenbelt, MD 20771 kenneth.w.wagner.1@gsfc.nasa.gov (301)286-9857 PRESENTATION A1

2. Introduction • This presentation describes how the gate array technology available at the time of our design was used to implement a one gigasample per second data acquisition system. • The mention or use of any product or technology in this presentation is not and shall not be used as an endorsement by the author, Goddard Space Flight Center (GSFC), or the National Aeronautics and Space Administration (NASA) or for any other purposes. PRESENTATION A1

3. The Science Objective • NASA Goddard Space Flight Center is building an instrument that will measure the height of the earth’s polar ice caps. • A satellite in polar orbit rapidly fires a laser at the earth. • The concept is to use the amount of time it takes for the photons to travel from the satellite’s laser, bounce off the earth’s surface, and return to the satellite’s detector. The detector generates a voltage based on the rate at which photons are striking it. • A portion of the laser’s outgoing photons are shunted back to the satellite’s detector. • A small portion of the laser’s photons strike the earth. • An even smaller portion of those photons return to the satellite’s detector. PRESENTATION A1

4. The Science Objective (continued) • We use the photon’s round-trip travel time and the trajectory of the satellite’s orbit to calculate the height of the earth’s surface. • Since the speed of light in a vacuum is 2.9979 × 108 meters per second, light travels 1 meter in 3.3 nanoseconds. • The project’s scientists determined that digitizing the detector’s voltage waveform to 8 bits at a rate of 1 Gigahertz (1 sample per nanosecond) would produce the necessary measurement accuracy. PRESENTATION A1

5. Top Level Requirements • Requirements imposed by the nature and concept of the design: • Low-earth (~600 kilometer) orbit in a 10 - 30 KRad environment. • That 10 - 30 KRad number would be reduced when ray-trace analysis is performed on this board in the instrument configuration and on further analysis of the orbit. • One 8-inch by 9-board with a fully redundant cold spare board. • As little power as possible and as little mass as possible (what the instrument managers always want). PRESENTATION A1

6. Electronics Requirements • What the electronics needs to be able to do: • Digitization of the detector’s voltage waveform at the time of the outgoing laser shot from the shunted outgoing photons. • Digitization of the detector’s voltage waveform at the approximated time of the incoming reflected photons. • Make an accurate measurement of the time between the outgoing laser shot and the incoming reflected photons’ arrival. • Filter the reflected photons’ waveform. • Search the filtered waveform for the exact time when the ground return was detected. PRESENTATION A1

7. Timing of the Acquisition Period Command to Fire Laser Fire Laser Return 200 usec + 5 usec ~4.5 milliseconds Data set 40 Hz Detector Signal Digitizer Data 195 usec ~ 10 Kbytes Search Range of 11 Km is ~70 Kbytes (approximately 4 Mbyte of 6 Mbyte used) Fire_Ack LIDAR Range Gate Delay Counter Started Delay Counter timeout & Period Counter start Period Counter timeout Amplifier Gain Selectable Transmit Gain Selectable Return Gain PRESENTATION A1

8. Initial Tradeoff • The first design step was to determine whether to digitize the entire detector waveform (that is, to digitize and save in memory the detector voltage waveform during outgoing laser time, during the time when the photons are traveling to and from the earth’s surface, and during the reflected photons’ arrival) or to only digitize the outgoing and reflected waveforms. • It was determined that it would be impractical to digitize only the outgoing and reflected waveforms due to difficulty in disabling and re-enabling the 1 GHz acquisition and accurately measuring the time that the acquisition was disabled. PRESENTATION A1

9. Analog to digital converter ASIC RAMBUS RAMBUS ASIC RAMBUS RAMBUS DSP Memory Requirementand Original Concept • Amount of memory required for digitization of the entire waveform: • Orbit: ~600 kilometers • At that orbit, it takes approximately 4.5 milliseconds for the laser’s photons to travel to the earth’s surface and back. • At 1 nanosecond per 8-bit sample, 4.5 million bytes of memory are needed to store the entire waveform. • Our original concept was to use Rambus technology. (Note that the block diagram doesn’t represent the actual quantity of each type of chip used.) PRESENTATION A1

10. Block Diagram of Original Concept PRESENTATION A1

11. Original Gate Array’s Function PRESENTATION A1

12. About Rambus • Rambus is a CMOS memory standard being used by the computer industry. • High-speed serial interface allowing for >500 Megabyte per second writes and reads. • Because it is serial, there is a low pin count • Small package size. • Rambus voltage levels for the inputs and outputs: • VREF = 1.9V to 2.5V • VLO = VREF - 0.80V to VREF - 0.35V • VHI = VREF + 0.35V to VREF + 0.80V • The voltage levels approximate the voltage swings of Emitter Coupled Logic (ECL). • [We had a difficult time obtaining from the manufacturers and from the standards writers information on the Rambus interface and information on macros and devices containing the Rambus controller module.] PRESENTATION A1

13. Original ASIC Development • We needed to design a gate array that would perform the necessary interfacing between the: • Analog-to-Digital Converter with its two 500-MHz ECL output channels • CMOS Rambuses with its 250-MHz clock, 500-MHz data lines, and odd logic-level I/O. • Executor block with a CMOS Digital Signal Processor at its center. • The VHDL code for this chip was nearly completely written. PRESENTATION A1

14. Ruling Out the Original Design • There are no programmable logic devices that can • meet the interface level and speed requirements of this design; nor • collect the Analog-to-Digital (A/D) converter data and write it to the Rambuses in bursts necessary to achieve the >500 Megabyte per second write rate. • ECL and Gallium Arsenide (GaAs) Application Specific Integrated Circuit (ASIC) manufacturers estimated the chance of successfully manufacturing such a chip the first time around at only 70% and the cost of the part would be huge. Additional spins at manufacturing the chip would also be expensive. PRESENTATION A1

15. The Completely Discrete Approach • With the single-ASIC approach ruled out, we decided to look at the opposite design approach: A completely discrete design approach. • Instead of collecting the data in a pair of ASICs to be written in serial bursts to Rambuses, the data would be collected in discrete ECL logic which would then be written to regular SRAMs. • We found some SRAMs manufactured by Lockheed Martin and White Microelectronics that would be useful for this approach. • 32-bit wide data buses • 128K 32-bit words per chip • 20 nanosecond cycle times PRESENTATION A1

16. Analog to digital converter ECL to TTL converters Actel FPGA SRAM ECL latch ECL latch ECL latch ECL latch SRAM ECL latch ECL latch ECL latch ECL latch Actel FPGA SRAM ECL latch ECL latch ECL latch ECL latch SRAM ECL latch ECL latch ECL latch ECL latch ECL to TTL converters Actel FPGA SRAM ECL latch ECL latch ECL latch ECL latch SRAM ECL latch ECL latch ECL latch ECL latch Actel FPGA SRAM ECL latch ECL latch ECL latch ECL latch SRAM ECL latch ECL latch ECL latch ECL latch ECL control logic DSP Completely Discrete Block Diagram • The A/D converter outputs would be saved into a series of ECL latches. While half the latches are receiving data, the other half would contain stable data to be written to the SRAMs through an FPGA. (Note that the block diagram doesn’t represent the actual quantity of each type of chip used.) PRESENTATION A1

17. Ruling Out the Completely Discrete Approach • An initial look found that • the board space required was enormous, and • the power used was huge, and • the pin count of the gate array would be too large for known devices because • it interfaced with lots of ECL latches, and • there are lots of data and address pins on the SRAMs PRESENTATION A1

18. Our Combination Solution • Our solution was to combine the two approaches: • Slow down the A/D converter outputs using discrete latches, until • the data is stable enough and slow enough to be latched into a gate array, where • in the gate array it is further latched to slow it down until the gate array can latch it into the slow SRAMs. • This lowered • the number of discrete latch chips to a manageable number for board area and power consumption and • the number of pins needed to interface to the SRAMs. PRESENTATION A1

19. Analog to digital converter ECL to TTL converters ChipExpress LPGA SRAM ECL latch ECL latch SRAM ECL latch ECL latch SRAM SRAM ECL to TTL converters ChipExpress LPGA SRAM ECL latch ECL latch SRAM ECL latch ECL latch SRAM SRAM ECL control logic DSP Block Diagram of Solution • (Note that block diagram doesn’t represent the actual quantity of each chiptype used.) PRESENTATION A1

20. Slowing Down the Data • ECL latches lower the data rate from the A/D converter’s pair of 500-MHz 8-bit channels down to 12 83.333-MHz 8-bit channels including individual “Data Readies.” • The 12 83.333-MHz 8-bit channels and Data Readies are converted from ECL to TTL levels. • Each of four gate arrays receives three of the 83.333-MHz (12 nanosecond) channels and their Data Readies. The data bytes arrive 120 degrees out of phase from each other (that is, data arrives to a gate array every 4 nanoseconds). • When a gate array has received four bytes through those channels, the gate array performs a write to a 32-bit SRAM at a frequency of 20.833 MHz. PRESENTATION A1

21. Other Gate Array Functions • The gate array also serves other purposes: • It decodes the A/D converter data from Gray to Binary. • It allows the Digital Signal Processor to access all the SRAMs • The address is decoded to access the interleaved data. • The 12 SRAMs appear to the processor as a single 1.5 Megabyte by 32 device. • The interleaved data is fetched from all the SRAMs in the order in which it was written to the SRAMs, not in the order in which it appears in a particular SRAM. PRESENTATION A1

22. The Selected Gate Array • The gate array we selected is the Chip Express QYH580 Laser Programmable Gate Array. • 304 pins allowed for the • data and data ready lines for three input 83.333 MHz channels • address, data, and control lines for three 128Kx32 SRAMs • address, data, and control lines for the DSP interface. • Only 10,000 of the part’s 80,000 NAND gates were used. The large array was needed to satisfy the I/O pin count requirement. • Careful synthesis, layout, and analysis allowed data to arrive every 4 nanoseconds of a 12-nanosecond period clock. • Since the hardest part of the routing was getting the 83.333 MHz channels from the board, through the input cell, and to the flip-flops, TMR architecture was used. Three flip-flops are used for each memory cell, with the majority of their outputs used as a cell’s value. PRESENTATION A1

23. Shortcomings of the Selected Part • There were some shortcomings of this part: • It is not a field programmable gate array. Therefore we must go to the manufacturer to program parts. Although turnaround is 1 to 4 weeks, that’s not the same as burning a part in our own lab. • Iterations in design are expensive. • We didn’t have the routing tools in-house. PRESENTATION A1

24. “Desirements” • Program Logic Device attributes that could help us in future designs: • Faster input cells. For our application: • Having an internal cell speed of 100 MHz or 250 MHz was not the driving force. • What we really needed was a part that could take in signals at 100 MHz or 250 MHz. • CMOS parts that can accommodate ECL inputs or user-specified inputs. • Field programmable. • A part that can handle the Rambus interface standard, especially since Rambus is being more widely used in the computer industry. PRESENTATION A1