A Survey of Logic Block Architectures. For Digital Signal Processing Applications. Presentation Outline. Considerations in Logic Block Design Computation Requirements Why Inefficiencies? Representative Logic Block Architectures Proposed Commercial Conclusions: What is suitable Where?.
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A Survey of Logic Block Architectures
For Digital Signal Processing Applications
COMPUTATION defines ARCHITECTURE
Some Representative Architectures
A Bit-Serial Adder which processes two bits at a time
Interface Block Diagram
A Digit-Serial Adder
A Digit-Serial Unsigned Multiplier
A Pipelined Digit-Serial Unsigned Multiplier For Y=8 bits
First Stage Module
Middle Stages Module
Last Stage Module
A Digit-Serial Signed Booth’s Pipelined Multiplier with Y=8
Table of Functions Implemented
The Structure of the LM
N=4 Unsigned
Multiplier
N=4 Signed
Multiplier
Two N=2
Multipliers
Bit-Level
Pipelined
Full Adder and Equations Showing
The Inverting Property
An optimal structure derived from
the property
Coarser ALU Like Architectures
Some Industry Architectures Designs
Processor-Programmable Logic Coupled Architecture