Status of measurements of FE-I4 SEU and PRD

1. Status of measurements of FE-I4 SEU and PRD A.Rozanov23.05.2011

2. Timing Problems • Syncronize with Spill signal instead of CPS cycle • Delete time stamps, DCS voltages and currents • Reduce readout to one DC per Spill • Result: able to readout without super-positions with the beam (except sporadic spills)

3. Timing Problems • Joern propose to write one RootDB file per spill, gain factor two in time • Since this weekend we switched to this mode • In this mode we have the time to double the readout and write the time stamp, so we can in principle correlate with beam information files • Software not yet ready for large volume analysis in this mode (handle of hunreds of files per run)

4. Hardware problems • On chip ID 28 Vdda1=Vdda2=1.3 V at start. During running go down to 1.0V, while setting is at 1.5V. Idda=142 mA Broken voltage regulator???? (Normal Vddd=1.5 v, Iddd=340mA) • Maurice will send Extension Board to CERN • Heintz and promise to find backup solution at CERN • Patrick Breugnon will try to exchange the IO/extension card in the IRRAD3 zone Wednesday 25 May 16:00 after 10-16 hours of cooling down during PS MD time

5. Preliminary SEU results chips# 27 and 28 • Run 28 • Type A (old) DC29 TDAC[1] and FDAC[1] • Type B (new) DC30 TDAC[1] and FDAC[1] • Statistics for ~230iterations ( ~920 spills ) • Normal SEU (<40 errors/bunch) • Coherent SEU(>40 errors/bunch )

6. Measurement of beam profile by SEU • Chip 27

7. Measurement of beam profile by SEU • Chip 28

8. Measurement of beam profile by diode (Maurice Glaser)

9. Normal SEU chip #27

10. Normal SEU chip #28 Two times more old SEU than in chip #27. Is it due to low Vdda = 1.10 V ??

11. Coherent SEU chip #27 14% coherent

12. Coherent SEU chip #28 6% coherent

13. History SEU chip #27 vs iteration Coherent mostly at some parts of the run

14. History SEU chip #28 vs iteration Coherent mostly at some parts of the run

15. Very preliminary SEU results chips# 27,28 • Normal SEU per spill ~20 10 10protons/cm2 • Chip 27 Type A 4.6 seu/spill/672bits • Chip 27 Type B 0.13 seu/spill/672bits • Chip 28 Type A 8.0 seu/spill/672bits • Chip 28 Type B 0.50 seu/spill/672bits • Low Vdda=1.2 V responsible for chip#28 increase ?? • Coherent SEU • compatible A and B • Chip 27 14% • Chip 28 6% • Coherent SEU are not reproducible in double readout. Glitches spoil SR readout ????

16. Radiation monitoring • Global Register readout often gives errors without beam • Errors seems to increase if in the same cycle we use also PR readout, so delete all PR readout from GR runs • Malte pointed out that Power OFF/ON cycle after chip configuration, but before start primitives helps to get out GR errors. Explanations ??? • Take GR data with beam pointed to GR run 36/chip27 • PRD counts 90-200 counts/spill , zero without beam • GR data run 37 chip28 • PRD counts zero or close, Vddaproblem ????

17. Conclusions • Need more analysis of existing data to understand the nature of coherent seu’s • New pixel latches (type B) looks very good • Vdda dependence of PR and GR SEU errors to be studied • More runs at PRD position needed

18. Spare

19. Measurements • Two FE-I4 chips installed in the PS beam Irrad3 • Chip ID28 (PC marslhc) • Chip ID27 (PC marnach) • Also chip SEU3D installed • Order in the beam ID27,ID28,SEU3D • Al foils on ID27 and SEU3 • Orientation: EOC on the top, beam traverse first PCB, second the chips • Horizontal beam position in the center (columns 39/40) • Vertical beam position 5mm down from the center (far from EOC) • Beam size 12x12 mm • Start beam Thursday 12 may 2011

20. Beam properties • Supercycle with 36x1.2=43.2 sec period • But sometimes is changing • Typical 2 bunches of 40 x 10 10 protons • But sometimes 3-4 bunches • Typical bunch positions: 4, 6,14,26 • Bunch length 400 msec • One iteration 2 (or 3) supercycles, 2-4 bunches per supercycle