Field Effect Transistors (1). Dr. Wojciech Jadwisienczak. EE314. http://www.plasticlogic.com. Q: How we can do this? A: A new generation of MOSFETs for plastic electronics. Construction of MOS NMOS and PMOS Types of MOS MOSFET Basic Operation Characteristics
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Dr. Wojciech Jadwisienczak
Q: How we can do this?
A: A new generation of MOSFETs for plastic electronics
Chapter 12: Field Effect Transistors pp. 544-577
Figure 4 – showing the lateral etching control offered by “digital” recess etching. In both micrographs, the depth of the recess is 30 nm. The micrograph on the left shows a “wide” gate recess with large lateral extent whilst the micrograph on the right shows a recess tightly defined around the gate footprint.
Figure 2 -120 nm footprint T-gate with self-aligned source and drain contacts.
JFET – Junction Field Effect Transistor
MOSFET - Metal Oxide Semiconductor Field Effect Transistor
n-channel MOSFET & p-channel MOSFET
Device characteristics depend on L,W, Thickness, doping levels
Operation in the Cutoff region
pn junction: forward bias, reverse bias
When vGS=0 then iD=0 until vGS>Vt0 (Vt0 –threshold voltage)
Operation in the Triode Region
For viDS<vGS-Vt0 and vGS>Vt0 the NMOS is operating in the
Resistor like characteristic
(R between S & D,
Used as voltage controlled R)
For small vDS, iD is proportional
to the excess voltagevGS-Vt0
Operation in the Saturation Region (vDS is increased)
iD is smaller
When vGD=Vt0 then the channel
thickness is 0 and
Device parameter KP for
NMOSFET is 50 mA/V2
id depends on vDS in saturation region
(approx: iD =const in saturation region)
It is constructed by interchanging the n and p regions of n-channel MOSFET.
How does operate
It is a graphical analysis similar to load-line analysis of pn diode.
We look for operating point
Taking iD=0 or vDS=0 we find out the quiescent operating point Q
The quiescent values
vin(t)=0 then iDQ=9 mA and vDSQ=11V
Points A & B intersection of curve and the load-line
(peak-to-peak amplitude is 2V)
The positive peak of the input occurs at the same time as the min. value of vDS. These are not symmetrical sinusoids! (nonlinear distortion)
Analysis of amplifier circuits is often undertaken in two steps:
(1) The dc circuit analysis to determine the Q point. It involves the
nonlinear equation or the load-line method. This is called bias
(2) Use a linear small-signal equivalent circuit to determine circuit
The fixed-plus self-bias circuit
Assume the VRG=0
For saturation region
Disregarded root for vGS<Vt0
Use only larger root for vGS and smaller for iD