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# Introduction to Sequential Logic Design PowerPoint PPT Presentation

Introduction to Sequential Logic Design. Latches. Terminology. A bistable memory device is the generic term for the elements we are studying. Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.

Introduction to Sequential Logic Design

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## Introduction to Sequential Logic Design

Latches

### Terminology

• A bistable memory device is the generic term for the elements we are studying.

• Latches and flip-flops (FFs) are the basic building blocks of sequential circuits.

• latch: bistable memory device with level sensitive triggering (no clock), watches all of its inputs continuously and changes its outputs at any time, independent of a clocking signal.

• flip-flop: bistable memory device with edge-triggering (with clock), samples its inputs, and changes its output only at times determined by a clocking signal.

### S-R latch

S sets the Q output to 1, R resets the Q output to 0.

If both R, S are negated, the latch remains in the state that it was forced to (like a bistable element).

QN is normally the complement of Q (but sometimes NOT).

### S-R latch operation

Metastability is possibleif S and R are negatedsimultaneously.

### S-R latch timing parameters

• Propagation delay

• Minimum pulse width

D

Q

C

Q

### D-latch operation

When C is asserted, Q follows the D input, the latch is “open” and the path (D-->Q) is “transparent”.

When C is negated, the latch “closes” and Q retains its last value.

### D-latch timing parameters

• Propagation delay (from C or D)

• Setup time (D before C edge)

• Hold time (D after C edge)

### S-R vs. D latches

• S-R

• Useful in control applications, “set” and “reset”

• S=R=1 problem

• Metastability problem when S, R are negated simultaneously, or a pulse applied to S, R is too short.

• D

• Store bits of information

• No S=R=1 problem

• Metastability still possible.

• Flip-flops