ECE 4110– Sequential Logic Design

ECE 4110– Sequential Logic Design Lecture #18 • Agenda • MSI Demultiplexers • MSI Tri-State Buffers • MSI Comparators • Announcements • HW #8 due • Next: No class Fall Break

Demultiplexer • Demultiplexer- this is the exact opposite of a Mux- a single input will be routed to a particular output pin depending on the Select settingex) truth table of DemultiplexerSel Y0 Y1 0 In 0 1 0 In

Demultiplexer • Demultiplexer- we can again use the behavior of an AND gate to “pass” or “block” the input signal- an AND gate is used for each Demux output

Demultiplexer • Demultiplexers in VHDL- Structural Model entity demux_1to4 is port (D : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end entity demux_1to4; architecture demux_1to4_arch of demux_1to4 is signal Sel_n : STD_LOGIC_VECTOR (1 downto 0); component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; begin U1 : inv1 port map (In1 => Sel(0), Out1 => Sel_n(0)); U2 : inv1 port map (In1 => Sel(1), Out1 => Sel_n(1)); U3 : and4 port map (In1 => D, In2 => Sel_n(1), In3 => Sel_n(0), In4 => EN, Out1 => Y(0)); U4 : and4 port map (In1 => D, In2 => Sel_n(1), In3 => Sel(0), In4 => EN, Out1 => Y(1)); U5 : and4 port map (In1 => D, In2 => Sel(1), In3 => Sel_n(0), In4 => EN, Out1 => Y(2)); U6 : and4 port map (In1 => D, In2 => Sel(1), In3 => Sel(0), In4 => EN, Out1 => Y(3)); end architecture demux_1to4_arch;

Demultiplexer • Demultiplexers in VHDL- Behavioral Model with High Z Outputs entity demux_1to4 is port (D : in STD_LOGIC; Sel : in STD_LOGIC_VECTOR (1 downto 0); EN : in STD_LOGIC; Y : out STD_LOGIC_VECTOR (3 downto 0)); end entity demux_1to4; architecture demux_1to4_arch of demux_1to4 is begin DEMUX : process (D, Sel, EN) begin if (EN = '1') then case (Sel) is when "00" => Y <= 'Z' & 'Z' & 'Z' & D; when "01" => Y <= 'Z' & 'Z' & D & 'Z'; when "10" => Y <= 'Z' & D & 'Z' & 'Z'; when "11" => Y <= D & 'Z' & 'Z' & 'Z'; when others => Y <= "ZZZZ"; end case; else Y <= "ZZZZ"; end if; end process DEMUX; end architecture demux_1to4_arch;

Tri-State Buffers • Tri-State Buffers- Provides either a Pass-Through or High Impedance Output depending on Enable Line- High Impedance (Z) allows the circuit to be connected to a line with multiple circuits driving/receiving- Using two Tri-State Buffers creates a "Bus Transceiver" - This is used for "Multi-Drop" Buses (i.e., many Drivers/Receivers on the same bus)ex) truth table of Tri-State Buffer ex) truth table of Bus Transceiver ENB Out Tx/RxMode 0 Z 0 Receive from Bus (Rx) 1 In 1 Drive Bus (Tx)

Tri-State Buffers • Tri-State Buffers in VHDL- 'Z' is a resolved value in the STD_LOGIC data type defined in Package STD_LOGIC- Z & 0 = 0- Z & 1 = 1- Z & L = L- Z & H = H TRISTATE: process (In1, ENB) begin if (ENB = '1') then Out1 <= 'Z'; else Out1 <= In1; end if; end process TRISTATE;

Comparators • Comparators- a circuit that compares digital values (i.e., Equal, Greater Than, Less Than)- we are considering Digital Comparators (Analog comparators also exist)- typically there will be 3-outputs, of which only one is asserted- whether a bit is EQ, GT, or LT is a Boolean expression - a 2-Bit Digital Comparator would look like: (A=B) (A>B) (A<B) A B EQ GT LT 0 0 1 0 0 EQ = (AB)' 0 1 0 0 1 GT = A·B' 1 0 0 1 0 LT = A'·B 1 1 1 0 0

Comparators • Non-Iterative Comparators- "Iterative" refers to a circuit make up of identical blocks. The first block performs its operation which produces a result used in the 2nd block and so on. - this can be thought of as a "Ripple" effect- Iterative circuits tend to be slower due to the ripple, but take less area- Non-Iterative circuits consist of combinational logic executing at the same time"Equality" - since each bit in a vector must be equal, the outputs of each bit's compare can be AND'd - for a 4-bit comparator: EQ = (A3B3)' · (A2B2)' ·(A1B1)' ·(A0B0)'

Comparators • Non-Iterative Comparators"Greater Than" - we can start at the MSB (n) and check whether An>Bn. - If it is, we are done and can ignore the rest of the LSB's. - If it is NOT, but they are equal, we need to check the next MSB bit (n-1) - to ensure the previous bit was equal, we include it in the next LSB's logic expression:Steps - GT = An·Bn' (this is ONLY true if An>Bn)- if it is NOT GT, we go to the n-1 bit assuming that An= Bn (An Bn)' - we consider An-1>Bn-1 only when An= Bn [i.e., (An Bn)' · (An-1·Bn-1') ] - we continue this process through all of the bits - 4-bit comparator GT = (A3·B3') + (A3B3)' ·(A2·B2') +(A3B3)' ·(A2B2)' ·(A1·B1') +(A3B3)' ·(A2B2)' ·(A1B1)' ·(A0·B0')

Comparators • Non-Iterative Comparators"Less Than" - since we assume that if the vectors are either EQ, GT, or LT, we can create LT using: LT = EQ' · GT' • Iterative Comparators- we can build an iterative comparator by passing signals between identical modules from MSB to LSB ex) module for 1-bit comparator EQout = (AB)' · EQin- EQout is fed into the EQin port of the next LSB module- the first iterative module has EQin set to '1'

Comparators • Comparators in VHDL- Structural Model entity comparator_4bit is port (In1, In2 : in STD_LOGIC_VECTOR (3 downto 0); EQ, LT, GT : out STD_LOGIC); end entity comparator_4bit; architecture comparator_4bit_arch of comparator_4bit is signal Bit_Equal : STD_LOGIC_VECTOR (3 downto 0); signal Bit_GT : STD_LOGIC_VECTOR (3 downto 0); signal In2_n : STD_LOGIC_VECTOR (3 downto 0); signal In1_and_In2_n : STD_LOGIC_VECTOR (3 downto 0); signal EQ_temp, GT_temp : STD_LOGIC; component xnor2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component or4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component nor2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and2 port (In1,In2: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and3 port (In1,In2,In3: in STD_LOGIC; Out1: out STD_LOGIC); end component; component and4 port (In1,In2,In3,In4: in STD_LOGIC; Out1: out STD_LOGIC); end component; component inv1 port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end component;

Comparators • Comparators in VHDL Cont… begin -- "Equal" Circuitry XN0 : xnor2 port map (In1(0), In2(0), Bit_Equal(0)); -- 1st level of XNOR tree XN1 : xnor2 port map (In1(1), In2(1), Bit_Equal(1)); XN2 : xnor2 port map (In1(2), In2(2), Bit_Equal(2)); XN3 : xnor2 port map (In1(3), In2(3), Bit_Equal(3)); AN0 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq); -- 2nd level of "Equal" Tree AN1 : and4 port map (Bit_Equal(0), Bit_Equal(1), Bit_Equal(2), Bit_Equal(3), Eq_temp); -- "Greater Than" Circuitry IV0 : inv1 port map (In2(0), In2_n(0)); -- creating In2' IV1 : inv1 port map (In2(1), In2_n(1)); IV2 : inv1 port map (In2(2), In2_n(2)); IV3 : inv1 port map (In2(3), In2_n(3)); AN2 : and2 port map (In1(3), In2_n(3), In1_and_In2_n(3)); -- creating In1 & In2' AN3 : and2 port map (In1(2), In2_n(2), In1_and_In2_n(2)); AN4 : and2 port map (In1(1), In2_n(1), In1_and_In2_n(1)); AN5 : and2 port map (In1(0), In2_n(0), In1_and_In2_n(0)); AN6 : and2 port map (Bit_Equal(3), In1_and_In2_n(2), Bit_GT(2)); AN7 : and3 port map (Bit_Equal(3), Bit_Equal(2), In1_and_In2_n(1), Bit_GT(1)); AN8 : and4 port map (Bit_Equal(3), Bit_Equal(2), Bit_Equal(1), In1_and_In2_n(0), Bit_GT(0)); OR0 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT); OR1 : or4 port map (In1_and_In2_n(3), Bit_GT(2), Bit_GT(1), Bit_GT(0), GT_temp); -- "Less Than" Circuitry ND0 : nor2 port map (EQ_temp, GT_temp, LT); end architecture comparator_4bit_arch;

Comparators • Comparators in VHDL- Behavioral Model entity comparator_4bit is port (In1, In2 : in STD_LOGIC_VECTOR (3 downto 0); EQ, LT, GT : out STD_LOGIC); end entity comparator_4bit; architecture comparator_4bit_arch of comparator_4bit is begin COMPARE : process (In1, In2) begin EQ <= '0'; LT <= '0'; GT <= '0'; -- initialize outputs to '0' if (In1 = In2) then EQ <= '1'; end if; -- Equal if (In1 < In2) then LT <= '1'; end if; -- Less Than if (In1 > In2) then GT <= '1'; end if; -- Greater Than end process COMPARE; end architecture comparator_4bit_arch;

ECE 4110– Sequential Logic Design