Ece 556 design automation of digital systems
This presentation is the property of its rightful owner.
Sponsored Links
1 / 40

ECE 556 Design Automation of Digital Systems PowerPoint PPT Presentation


  • 171 Views
  • Uploaded on
  • Presentation posted in: General

ECE 556 Design Automation of Digital Systems. By Prof. Charlie Chung-Ping Chen ECE Department UW-Madison. Outline. Microprocessor Technology Trends and Design Issues Interconnect delay trends Circuit type trends Research summary. Microprocessor Design Challenges.

Download Presentation

ECE 556 Design Automation of Digital Systems

An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -

Presentation Transcript


ECE 556 Design Automation of Digital Systems

By

Prof. Charlie Chung-Ping Chen

ECE Department

UW-Madison


Outline

  • Microprocessor Technology Trends and Design Issues

  • Interconnect delay trends

  • Circuit type trends

  • Research summary


Microprocessor Design Challenges

  • High performance ( > 500 Mhz)

  • Low cost (< $100)

  • Low power consumption (< 10W mobile)

  • More functionality (KNI MMX)

  • Shorter time to market (< 18 months)

  • Satisfies different market segments (server, sub-$1000)

  • Competition

  • ….

Mission Impossible!


Tentative Class Schedule

  • Technology Trends (1 class)

  • Interconnect Modeling and Optimization: (1 week)

    • basic routing: maze-routing

    • wire-sizing, buffer-sizing, buffer-insertion

  • Introduction to Verilog (1 week)

  • Linear programming and Introduction to C and C++ language (1 week)

  • Routing: (2 week)

    • Clock routing (0.6 week)

    • Global and channel routing, Tree routing (1.4 week)

  • Timing Analysis (1 week)

    • Delay Characterization, Power Characterization

    • PERL and Latch based timing analysis

  • Partitioning and Placement (1.5 week)

  • Floorplanning (1 week)


Deal With It!

  • Higher clock frequencies

  • New processes: 0.18 micron, copper

  • Architecture level

    • Superscalar, super-pipeline, out-of-order execution, speculative execution, EPIC, VLIW, ILP, multi-thread

  • Circuit level

    • Aggressive dynamic circuits synthesis

    • Sizing, parallel re-powering, logic minimization

  • Physical Design

    • Performance-driven place and route, floorplaning

    • Wire-sizing, buffer-sizing, buffer-insertion


Moore's First Law


"Extrapolated" Year 1999 wafer size


Moore's Second Law


Size of Team Explodes


Process Overview

  • New process (0.18 um)

    • High aspect ratio

    • Low sheet rho (resistance)

    • Low-e dielectric (capacitance) (3.55 vs. 4.10)

    • Good Electromigration property

    • 6 metal layers

      • M1 tight pitch for density (X-cap)

      • M2-M3 middle pitch for density & performance (X-cap)

      • M4-M6 high pitch (low resistance) for performance (Inductance)

  • Future

    • Copper - Less resistance more inductance effect

    • SOI - the M1 coupling strange


0.25 Micron, 5 Layer Technology

IEDM 96


0.18 Micron, 6 Layer Technology

M6

M5

M4

M3

M2

M1

IEDM 99


Gate Delay .v.s. Scaling

IEDM 99


Interconnect Resistance Grows Super Linearly

IEDM 99


Interconnect Delay Trend

IEDM 99


Interconnect Complicated Design Flow

Architecture

RTL

Logic

Over tens of iterations!

Gate

Layout


Signal Integrity A new design challenge

CrossCap

Crosstalk

1

2


|H(jw)|

PRIMA=PVL=EXACT

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

|H(jw)|

PVL

PRIMA

EXACT

0

0.5

1

1.5

2

-3

Inductance effect emerging

  • An old clock tree

    • Freq domain up to 1Ghz

    • PVL and PRIMA with order 16 find the exact

  • A newer ckt, a section of power grid

    • Has L’s

    • PVL and PRIMA with 60th order

    • Frequencies more than 0.6 Ghz are not covered

Frequency (Ghz)


-400

TIM

Multi-Point PRIMA-34

-450

-500

PRIMA-80

PVL-80

-550

80

70

72

74

76

78

Some MOR result


Model order reduction

  • We need efficient tools to analyze the interconnect dominant circuits (power grids, packages etc.) accurately in a reasonable amount of time

  • Promising Model Order Reduction (MOR) techniques

Nonlinear Elements

Nonlinear Elements

Linear Elements

Reduced Model


Power Consumption

  • P ~ C V2 f, where

    • C = Capacitance ~ Area

    • V = Supply Voltage

    • f = Operation Frequency


Power Trend


Supply Voltage Trends


Deal With It!

  • Interconnect

    • Wire- and Repeater- Sizing

    • Repeater Insertion

    • Performance-driven noise-aware routing

    • New material: Low resistance (Cooper), Low k material (SiN2)

  • Gates

    • Gate Sizing

    • New Circuit Exploration - Dynamic Circuit, Dual Vt

  • ….


Standby Power Trend


Threshold Voltage v.s. Supply Voltage


Vt v.s. Delay


Dual Vt circuit

High Vt

Low Vt


Aggressive circuit styles


Clock delayed and Self-resetting dynamic circuits


Process limitations


  • Login