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ECE 679: Digital Systems Engineering

ECE 679: Digital Systems Engineering. Patrick Chiang Office Hours: 1-2PM Mon-Thurs GLSN 100. Class Introductions. Who am I Who are you. Class Basics. Class basics 4 Homeworks (%20) (groups of 2) Midterm (%40) Final Project (%40) 4-page IEEE report 10 minute presentation (groups of 2)

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ECE 679: Digital Systems Engineering

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  1. ECE 679: Digital Systems Engineering Patrick Chiang Office Hours: 1-2PM Mon-Thurs GLSN 100

  2. Class Introductions • Who am I • Who are you

  3. Class Basics • Class basics • 4 Homeworks (%20) (groups of 2) • Midterm (%40) • Final Project (%40) • 4-page IEEE report • 10 minute presentation (groups of 2) • Guest lecture (Dr. Frank O’Mahony) • Intel Research Labs (May 4th) • Intel Field Trip (June 7th) TBD • Presentations of 1-2 best project reports

  4. Class Homework • Homework • Skim Dally/Poulton “Digital Systems Engineering” • Chapter 3 • Skim Overview Paper: http://mos.stanford.edu/papers/mh_micro_98.pdf • Includes running Stat Eye • Oregon State Matlab (eecs.oregonstate.edu/it) • www.stateye.org • Problem Set #1 • rlc files -- ~pchiang/hspice (rlc_spice_deck; rlc.rlc) • Spice models -- ~pchiang/hspice/process_files/ • 130nm to 22nm • Simulator lang = spice • Spectre models – DEFINE gpdk090 /nfs/guille/analog/c/cdsmgr/process/gpdk090_v3.8/libs.cdb/gpdk090

  5. What does this mean for analog designers? • Ever build an ADC? • Ever wonder what to do with the digital bits? 8-16 bits@ 100MHz, 200MHz, 400MHz Goes to Vector analyzer Analog • Why does this clock rate not increase? • What really is this output doing? Whereis it going? Fs = 600MHz

  6. Brief Summary • Introduction to the area • Why serial links are important • What are the current technology trends/limitations

  7. IBM Processor y r o CPU CPU m e M From/to other High-speed I/Os subsystems (e.g. backplane) TransmitterOutput ReceiverInput Router Backplane(1m, FR4) 4Gb/s Low Power, Area Efficient Serial Links • Interconnection betweendifferent chips • Transmitter Equalization • Receiver Offset Cancellation 4Gb/s Transmitter Output, 1m 2000 0.25um Testchip 2001 0.25um Testchip • Ming-Ju E. Lee, William J. Dally, John W. Poulton, Patrick Chiang, Stephen F. Greenwood. An 84-mW 4Gb/s Clock and Data Recovery Circuit for Serial Link Applications. VLSI Circuits Symposium, Kyoto, Japan, June 2001, pp. 149-152. • Ming-Ju E. Lee, William Dally, Patrick Chiang. Low-Power Area-Efficient High-Speed I/O Circuit Techniques. IEEE Journal of Solid-State Circuits, November 2000, Vol. 35, No. 11, pp. 1591-1599. 4Gb/s Transmitter Output, Equalized 4Gb/s Transmitter Output

  8. 250ps v t 50ps v t 4Gb/s Eye Diagram 20Gb/s Eye Diagram Scaling Serial Links:From 4Gb/s->20Gb/s • Thesis: Develop 20Gb/s Serial Link • Area: 500um x 500um • Power: 200mW/link • 1 bit time = 1FO4 • Timing uncertainty becomes KEY issue

  9. No post-PLLClock Buffers Transmitter Block Diagram

  10. Test Chip Test Interface 10GHz PLL TestStructures PRBS Check PhaseInterpolators 700um RX DLL Clock Recovery TX TransmitterMuxing PRBS Gen 1.1mm • UMC 1.2V, 0.13um CMOS(single Vt) • Die size 700um x 1.15mm • 50 Ohm Pad Termination using Wafer Probes

  11. PLL Measurements Power Spectrum Q=10 Jitter Q=5 Jitter (c) • Jitter limited by 1.25GHz input reference clock • HP 8133A input clock (1.2ps RMS, 8.9ps pk-pk)

  12. Eye Diagram Jitter 2.2ps RMS 15.6ps pk-pk • Data Rate = 19.2Gb/s • Voltage ripple caused by lack of current source at differential pair tail node

  13. High Speed Transmitter Comparisons A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOSusing a Tri-State Binary PD with 100ps Gated Digital Output T. Masuda, et. al., ISSCC 2007. A full-rate 10Gb/s transceiver core employing a tri-state binary PDwith 100ps gated digital output is implemented in a 90nm CMOS process. Direct drive from the VCO is utilized to eliminate the 10GHz clock buffer current. The RX exhibits a recovered jitterof 906fs(rms) and an input sensitivity of 5.9mV. The TX generatesa jitter of 5mUI(rms). The chip consumes 250mW.

  14. MultiphasePLL ck[0] ck[1] ck[2] ck[3] • Static Phase Offset • Power Supply Sensitivity D[0] D[1] In Data20Gb/s D[2] Pre-Amp D[3] Conventional Serial Link Receivers • Conventional architectures also use multi-phase PLL

  15. Equalizing Path 2nd Generation Transmitter • 2-Tap Equalizer implemented for compensatingfor channel losses • Achieve 50ps analog delay with CML buffers

  16. Fabrication: Test Chip 2006 0.13um Test Chip 450um • ST Microelectronics 0.13um test chip • 307mW / transceiver • 0.46mm^2 • 20mV input sensitivity 350um Transmitter 500um 600um Receiver

  17. Results 80mV 20Gb/sIdeal Channel All Results Single-Ended 43ps 33mV 20Gb/s-6.5dB @ 10GHz 37ps

  18. Results (cont’d) 20Gb/sIdeal Channelwith α=0.37 72mV 36.4ps 62mV 20Gb/s-6.5dB @ 10GHzwith α=0.37 35ps

  19. Rationale for Multi-cores • Next generation computing – Multi-core Processing • i.e. multiple, parallel DSPs (i.e. MACs) • Why we cannot achieve faster frequencies? • Wire delays don’t scale like transistors • Power increases exponentially(when pushing process technology) • Timing margins degraded by • Variability • Power supply noise • Digital crosstalk • NOTE: More independent threads require more memory bandwidth Intel, 80 Cores, ISSCC 2007

  20. Research: Explore Parallel Serial Links • Serial Links also exhibit the same characteristics • Channel losses get worse • Power consumption increases significantly with bandwidth • Timing precision limited by: • Static Phase Offset (process variation) • Power-supply Induced Jitter • Interchannel Crosstalk • Serial Links need to to also push for high amounts of parallelism • How is this different than conventional link design? • Channel equalization becomes more difficult • Adjacent channel crosstalk • Difficult channel estimation problem (power, flexibility, data-rate, equalizer design, channel, distance) • Amortize Clock Power for Multiple Links • Distributed resonant clocking of analog/mixed-signal front-end’s

  21. Problem of IO • 2500 pins / 2 = 1200 Differential pins • Assume 10Gbs / link = 12 Tb/s Bandwidth • 100mW/Gb(bandwidth) = 120W

  22. Stateye Playing • Fun with Stat-Eye • 5Gb/s -> 10Gb/s • Worse Channels • Worse timing jitter • Homework examples

  23. Next Time • Telegrapher’s Equation • Reflection coefficients • Channel Models • Skin Effect • Dielectric constant • vias

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